mirror of https://github.com/YosysHQ/yosys.git
Fixed off-by-one bug in "hierarchy -check" for positional module args
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@ -206,9 +206,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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for (auto &conn : cell->connections())
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for (auto &conn : cell->connections())
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if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
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if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
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int id = atoi(conn.first.c_str()+1);
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int id = atoi(conn.first.c_str()+1);
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if (id < 0 || id >= GetSize(mod->ports))
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if (id <= 0 || id > GetSize(mod->ports))
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log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n",
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log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n",
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log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id + 1);
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log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id);
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} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
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} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
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log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
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log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
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log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
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log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
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