mirror of https://github.com/YosysHQ/yosys.git
backend/firrtl: Convert to use Mem helpers.
This commit is contained in:
parent
ef4ddfacf3
commit
b6721aa9d8
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@ -23,6 +23,7 @@
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#include "kernel/celltypes.h"
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#include "kernel/cellaigs.h"
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#include "kernel/log.h"
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#include "kernel/mem.h"
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#include <algorithm>
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#include <string>
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#include <vector>
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@ -366,126 +367,6 @@ struct FirrtlWorker
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RTLIL::Design *design;
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std::string indent;
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// Define read/write ports and memories.
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// We'll collect their definitions and emit the corresponding FIRRTL definitions at the appropriate point in module construction.
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// For the moment, we don't handle $readmemh or $readmemb.
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// These will be part of a subsequent PR.
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struct read_port {
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string name;
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bool clk_enable;
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bool clk_parity;
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bool transparent;
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RTLIL::SigSpec clk;
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RTLIL::SigSpec ena;
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RTLIL::SigSpec addr;
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read_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr) : name(name), clk_enable(clk_enable), clk_parity(clk_parity), transparent(transparent), clk(clk), ena(ena), addr(addr) {
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// Current (3/13/2019) conventions:
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// generate a constant 0 for clock and a constant 1 for enable if they are undefined.
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if (!clk.is_fully_def())
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this->clk = SigSpec(State::S0);
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if (!ena.is_fully_def())
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this->ena = SigSpec(State::S1);
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}
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string gen_read(const char * indent) {
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string addr_expr = make_expr(addr);
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string ena_expr = make_expr(ena);
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string clk_expr = make_expr(clk);
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string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
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string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
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string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
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return addr_str + ena_str + clk_str;
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}
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};
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struct write_port : read_port {
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RTLIL::SigSpec mask;
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write_port(string name, bool clk_enable, bool clk_parity, bool transparent, RTLIL::SigSpec clk, RTLIL::SigSpec ena, RTLIL::SigSpec addr, RTLIL::SigSpec mask) : read_port(name, clk_enable, clk_parity, transparent, clk, ena, addr), mask(mask) {
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if (!clk.is_fully_def())
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this->clk = SigSpec(RTLIL::Const(0));
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if (!ena.is_fully_def())
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this->ena = SigSpec(RTLIL::Const(0));
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if (!mask.is_fully_def())
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this->ena = SigSpec(RTLIL::Const(1));
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}
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string gen_read(const char * /* indent */) {
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log_error("gen_read called on write_port: %s\n", name.c_str());
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return stringf("gen_read called on write_port: %s\n", name.c_str());
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}
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string gen_write(const char * indent) {
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string addr_expr = make_expr(addr);
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string ena_expr = make_expr(ena);
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string clk_expr = make_expr(clk);
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string mask_expr = make_expr(mask);
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string mask_str = stringf("%s%s.mask <= %s\n", indent, name.c_str(), mask_expr.c_str());
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string addr_str = stringf("%s%s.addr <= %s\n", indent, name.c_str(), addr_expr.c_str());
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string ena_str = stringf("%s%s.en <= %s\n", indent, name.c_str(), ena_expr.c_str());
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string clk_str = stringf("%s%s.clk <= asClock(%s)\n", indent, name.c_str(), clk_expr.c_str());
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return addr_str + ena_str + clk_str + mask_str;
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}
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};
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/* Memories defined within this module. */
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struct memory {
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Cell *pCell; // for error reporting
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string name; // memory name
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int abits; // number of address bits
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int size; // size (in units) of the memory
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int width; // size (in bits) of each element
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int read_latency;
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int write_latency;
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vector<read_port> read_ports;
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vector<write_port> write_ports;
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std::string init_file;
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std::string init_file_srcFileSpec;
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string srcLine;
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memory(Cell *pCell, string name, int abits, int size, int width) : pCell(pCell), name(name), abits(abits), size(size), width(width), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec("") {
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// Provide defaults for abits or size if one (but not the other) is specified.
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if (this->abits == 0 && this->size != 0) {
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this->abits = ceil_log2(this->size);
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} else if (this->abits != 0 && this->size == 0) {
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this->size = 1 << this->abits;
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}
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// Sanity-check this construction.
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if (this->name == "") {
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log_error("Nameless memory%s\n", this->atLine());
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}
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if (this->abits == 0 && this->size == 0) {
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log_error("Memory %s has zero address bits and size%s\n", this->name.c_str(), this->atLine());
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}
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if (this->width == 0) {
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log_error("Memory %s has zero width%s\n", this->name.c_str(), this->atLine());
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}
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}
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// We need a default constructor for the dict insert.
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memory() : pCell(0), read_latency(0), write_latency(1), init_file(""), init_file_srcFileSpec(""){}
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const char *atLine() {
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if (srcLine == "") {
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if (pCell) {
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auto p = pCell->attributes.find(ID::src);
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srcLine = " at " + p->second.decode_string();
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}
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}
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return srcLine.c_str();
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}
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void add_memory_read_port(read_port &rp) {
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read_ports.push_back(rp);
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}
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void add_memory_write_port(write_port &wp) {
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write_ports.push_back(wp);
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}
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void add_memory_file(std::string init_file, std::string init_file_srcFileSpec) {
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this->init_file = init_file;
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this->init_file_srcFileSpec = init_file_srcFileSpec;
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}
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};
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dict<string, memory> memories;
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void register_memory(memory &m)
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{
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memories[m.name] = m;
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}
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void register_reverse_wire_map(string id, SigSpec sig)
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{
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for (int i = 0; i < GetSize(sig); i++)
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@ -658,7 +539,9 @@ struct FirrtlWorker
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{
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std::string moduleFileinfo = getFileinfo(module);
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f << stringf(" module %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
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vector<string> port_decls, wire_decls, cell_exprs, wire_exprs;
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vector<string> port_decls, wire_decls, mem_exprs, cell_exprs, wire_exprs;
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std::vector<Mem> memories = Mem::get_all_memories(module);
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for (auto wire : module->wires())
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{
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@ -686,14 +569,15 @@ struct FirrtlWorker
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for (auto cell : module->cells())
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{
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static Const ndef(0, 0);
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Const ndef(0, 0);
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// Is this cell is a module instance?
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if (cell->type[0] != '$')
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if (module->design->module(cell->type))
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{
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process_instance(cell, wire_exprs);
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continue;
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}
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// Not a module instance. Set up cell properties
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bool extract_y_bits = false; // Assume no extraction of final bits will be required.
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int a_width = cell->parameters.at(ID::A_WIDTH, ndef).as_int(); // The width of "A"
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@ -1004,126 +888,9 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in(ID($mem)))
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if (cell->is_mem_cell())
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{
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string mem_id = make_id(cell->name);
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int abits = cell->parameters.at(ID::ABITS).as_int();
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int width = cell->parameters.at(ID::WIDTH).as_int();
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int size = cell->parameters.at(ID::SIZE).as_int();
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memory m(cell, mem_id, abits, size, width);
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int rd_ports = cell->parameters.at(ID::RD_PORTS).as_int();
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int wr_ports = cell->parameters.at(ID::WR_PORTS).as_int();
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Const initdata = cell->parameters.at(ID::INIT);
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for (State bit : initdata.bits)
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if (bit != State::Sx)
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log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell));
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Const rd_clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE);
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Const wr_clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE);
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Const wr_clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY);
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int offset = cell->parameters.at(ID::OFFSET).as_int();
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if (offset != 0)
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log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell));
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for (int i = 0; i < rd_ports; i++)
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{
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if (rd_clk_enable[i] != State::S0)
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log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
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SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(i*abits, abits);
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SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(i*width, width);
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string addr_expr = make_expr(addr_sig);
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string name(stringf("%s.r%d", m.name.c_str(), i));
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bool clk_enable = false;
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bool clk_parity = true;
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bool transparency = false;
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SigSpec ena_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
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SigSpec clk_sig = RTLIL::SigSpec(RTLIL::State::S0, 1);
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read_port rp(name, clk_enable, clk_parity, transparency, clk_sig, ena_sig, addr_sig);
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m.add_memory_read_port(rp);
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cell_exprs.push_back(rp.gen_read(indent.c_str()));
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register_reverse_wire_map(stringf("%s.data", name.c_str()), data_sig);
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}
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for (int i = 0; i < wr_ports; i++)
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{
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if (wr_clk_enable[i] != State::S1)
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log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
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if (wr_clk_polarity[i] != State::S1)
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log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
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string name(stringf("%s.w%d", m.name.c_str(), i));
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bool clk_enable = true;
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bool clk_parity = true;
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bool transparency = false;
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SigSpec addr_sig =cell->getPort(ID::WR_ADDR).extract(i*abits, abits);
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string addr_expr = make_expr(addr_sig);
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SigSpec data_sig =cell->getPort(ID::WR_DATA).extract(i*width, width);
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string data_expr = make_expr(data_sig);
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SigSpec clk_sig = cell->getPort(ID::WR_CLK).extract(i);
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string clk_expr = make_expr(clk_sig);
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SigSpec wen_sig = cell->getPort(ID::WR_EN).extract(i*width, width);
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string wen_expr = make_expr(wen_sig[0]);
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for (int i = 1; i < GetSize(wen_sig); i++)
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if (wen_sig[0] != wen_sig[i])
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log_error("Complex write enable on port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
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SigSpec mask_sig = RTLIL::SigSpec(RTLIL::State::S1, 1);
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write_port wp(name, clk_enable, clk_parity, transparency, clk_sig, wen_sig[0], addr_sig, mask_sig);
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m.add_memory_write_port(wp);
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cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), name.c_str(), data_expr.c_str()));
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cell_exprs.push_back(wp.gen_write(indent.c_str()));
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}
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register_memory(m);
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continue;
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}
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if (cell->type.in(ID($memwr), ID($memrd), ID($meminit)))
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{
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std::string cell_type = fid(cell->type);
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std::string mem_id = make_id(cell->parameters[ID::MEMID].decode_string());
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int abits = cell->parameters.at(ID::ABITS).as_int();
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int width = cell->parameters.at(ID::WIDTH).as_int();
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memory *mp = nullptr;
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if (cell->type == ID($meminit) ) {
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log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str());
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} else {
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// It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
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auto addrSig = cell->getPort(ID::ADDR);
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auto dataSig = cell->getPort(ID::DATA);
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auto enableSig = cell->getPort(ID::EN);
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auto clockSig = cell->getPort(ID::CLK);
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Const clk_enable = cell->parameters.at(ID::CLK_ENABLE);
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Const clk_polarity = cell->parameters.at(ID::CLK_POLARITY);
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// Do we already have an entry for this memory?
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if (memories.count(mem_id) == 0) {
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memory m(cell, mem_id, abits, 0, width);
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register_memory(m);
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}
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mp = &memories.at(mem_id);
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int portNum = 0;
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bool transparency = false;
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string data_expr = make_expr(dataSig);
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if (cell->type.in(ID($memwr))) {
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portNum = (int) mp->write_ports.size();
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write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig);
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mp->add_memory_write_port(wp);
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cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str()));
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cell_exprs.push_back(wp.gen_write(indent.c_str()));
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} else if (cell->type.in(ID($memrd))) {
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portNum = (int) mp->read_ports.size();
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read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig);
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mp->add_memory_read_port(rp);
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cell_exprs.push_back(rp.gen_read(indent.c_str()));
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register_reverse_wire_map(stringf("%s.data", rp.name.c_str()), dataSig);
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}
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}
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// Will be handled below, as part of a Mem.
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continue;
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}
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@ -1145,12 +912,6 @@ struct FirrtlWorker
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continue;
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}
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// This may be a parameterized module - paramod.
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if (cell->type.begins_with("$paramod"))
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{
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process_instance(cell, wire_exprs);
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continue;
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}
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if (cell->type == ID($shiftx)) {
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// assign y = a[b +: y_width];
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// We'll extract the correct bits as part of the primop.
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@ -1215,6 +976,82 @@ struct FirrtlWorker
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log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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}
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for (auto &mem : memories) {
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string mem_id = make_id(mem.memid);
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Const init_data = mem.get_init_data();
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if (!init_data.is_fully_undef())
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log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(mem.memid));
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if (mem.start_offset != 0)
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log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(mem.memid));
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for (int i = 0; i < GetSize(mem.rd_ports); i++)
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{
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auto &port = mem.rd_ports[i];
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string port_name(stringf("%s.r%d", mem_id.c_str(), i));
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if (port.clk_enable)
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log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
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std::ostringstream rpe;
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string addr_expr = make_expr(port.addr);
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string ena_expr = make_expr(State::S1);
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string clk_expr = make_expr(State::S0);
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rpe << stringf("%s%s.addr <= %s\n", indent.c_str(), port_name.c_str(), addr_expr.c_str());
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rpe << stringf("%s%s.en <= %s\n", indent.c_str(), port_name.c_str(), ena_expr.c_str());
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rpe << stringf("%s%s.clk <= asClock(%s)\n", indent.c_str(), port_name.c_str(), clk_expr.c_str());
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cell_exprs.push_back(rpe.str());
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register_reverse_wire_map(stringf("%s.data", port_name.c_str()), port.data);
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}
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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auto &port = mem.wr_ports[i];
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string port_name(stringf("%s.w%d", mem_id.c_str(), i));
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if (!port.clk_enable)
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log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
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if (!port.clk_polarity)
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log_error("Negedge write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
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for (int i = 1; i < GetSize(port.en); i++)
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if (port.en[0] != port.en[i])
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log_error("Complex write enable on port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid));
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std::ostringstream wpe;
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string data_expr = make_expr(port.data);
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string addr_expr = make_expr(port.addr);
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string ena_expr = make_expr(port.en[0]);
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string clk_expr = make_expr(port.clk);
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string mask_expr = make_expr(State::S1);
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wpe << stringf("%s%s.data <= %s\n", indent.c_str(), port_name.c_str(), data_expr.c_str());
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wpe << stringf("%s%s.addr <= %s\n", indent.c_str(), port_name.c_str(), addr_expr.c_str());
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wpe << stringf("%s%s.en <= %s\n", indent.c_str(), port_name.c_str(), ena_expr.c_str());
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wpe << stringf("%s%s.clk <= asClock(%s)\n", indent.c_str(), port_name.c_str(), clk_expr.c_str());
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wpe << stringf("%s%s.mask <= %s\n", indent.c_str(), port_name.c_str(), mask_expr.c_str());
|
||||
|
||||
cell_exprs.push_back(wpe.str());
|
||||
}
|
||||
|
||||
std::ostringstream me;
|
||||
|
||||
me << stringf(" mem %s:\n", mem_id.c_str());
|
||||
me << stringf(" data-type => UInt<%d>\n", mem.width);
|
||||
me << stringf(" depth => %d\n", mem.size);
|
||||
for (int i = 0; i < GetSize(mem.rd_ports); i++)
|
||||
me << stringf(" reader => r%d\n", i);
|
||||
for (int i = 0; i < GetSize(mem.wr_ports); i++)
|
||||
me << stringf(" writer => w%d\n", i);
|
||||
me << stringf(" read-latency => %d\n", 0);
|
||||
me << stringf(" write-latency => %d\n", 1);
|
||||
me << stringf(" read-under-write => undefined\n");
|
||||
|
||||
mem_exprs.push_back(me.str());
|
||||
}
|
||||
|
||||
for (auto conn : module->connections())
|
||||
{
|
||||
string y_id = next_id();
|
||||
|
@ -1316,22 +1153,9 @@ struct FirrtlWorker
|
|||
|
||||
f << stringf("\n");
|
||||
|
||||
// If we have any memory definitions, output them.
|
||||
for (auto kv : memories) {
|
||||
memory &m = kv.second;
|
||||
f << stringf(" mem %s:\n", m.name.c_str());
|
||||
f << stringf(" data-type => UInt<%d>\n", m.width);
|
||||
f << stringf(" depth => %d\n", m.size);
|
||||
for (int i = 0; i < (int) m.read_ports.size(); i += 1) {
|
||||
f << stringf(" reader => r%d\n", i);
|
||||
}
|
||||
for (int i = 0; i < (int) m.write_ports.size(); i += 1) {
|
||||
f << stringf(" writer => w%d\n", i);
|
||||
}
|
||||
f << stringf(" read-latency => %d\n", m.read_latency);
|
||||
f << stringf(" write-latency => %d\n", m.write_latency);
|
||||
f << stringf(" read-under-write => undefined\n");
|
||||
}
|
||||
for (auto str : mem_exprs)
|
||||
f << str;
|
||||
|
||||
f << stringf("\n");
|
||||
|
||||
for (auto str : cell_exprs)
|
||||
|
|
Loading…
Reference in New Issue