mirror of https://github.com/YosysHQ/yosys.git
Do not detect fsm state registers with init attribute
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@ -110,6 +110,8 @@ static bool check_state_users(RTLIL::SigSpec sig)
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static void detect_fsm(RTLIL::Wire *wire)
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{
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if (wire->attributes.count("\\init") > 0)
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return;
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if (wire->attributes.count("\\fsm_encoding") > 0 || wire->width <= 1)
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return;
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if (sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire))))
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