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Removed TODO list from README file
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README
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README
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@ -366,33 +366,3 @@ from SystemVerilog:
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- The keywords "always_comb", "always_ff" and "always_latch", "logic" and
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- The keywords "always_comb", "always_ff" and "always_latch", "logic" and
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"bit" are supported.
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"bit" are supported.
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Roadmap / Large-scale TODOs
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===========================
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- Technology mapping for real-world applications
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- Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
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- Implement SAT-based formal equivialence checker
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- Write equiv pass based on hint-based register mapping
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- Re-implement Verilog frontend (far future)
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- cleaner (easier to use, harder to use wrong) AST format
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- pipeline of well structured AST transformations
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- true contextual name lookup
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Other Unsorted TODOs
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====================
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- Implement missing Verilog 2005 features:
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- Support for real (float) const. expressions and parameters
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- Ignore what needs to be ignored (e.g. drive and charge strengths)
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- Check standard vs. implementation to identify missing features
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- Miscellaneous TODO items:
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- Add brief source code documentation to most passes and kernel code
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- Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
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