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read_aiger: consistency between ascii and binary

This commit is contained in:
Eddie Hung 2020-01-07 09:32:34 -08:00
parent 5d9050a955
commit b57f692a9e
1 changed files with 7 additions and 13 deletions
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20
frontends/aiger/aigerparse.cc
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@ -496,13 +496,14 @@ void AigerReader::parse_aiger_ascii()
unsigned l1, l2, l3; unsigned l1, l2, l3;
// Parse inputs // Parse inputs
int digits = ceil(log10(I));
for (unsigned i = 1; i <= I; ++i, ++line_count) { for (unsigned i = 1; i <= I; ++i, ++line_count) {
if (!(f >> l1)) if (!(f >> l1))
log_error("Line %u cannot be interpreted as an input!\n", line_count); log_error("Line %u cannot be interpreted as an input!\n", line_count);
log_debug2("%d is an input\n", l1); log_debug2("%d is an input\n", l1);
log_assert(!(l1 & 1)); // Inputs can't be inverted RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1));
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
wire->port_input = true; wire->port_input = true;
module->connect(createWireIfNotExists(module, l1 << 1), wire);
inputs.push_back(wire); inputs.push_back(wire);
} }
@ -552,25 +553,18 @@ void AigerReader::parse_aiger_ascii()
} }
// Parse outputs // Parse outputs
digits = ceil(log10(O));
for (unsigned i = 0; i < O; ++i, ++line_count) { for (unsigned i = 0; i < O; ++i, ++line_count) {
if (!(f >> l1)) if (!(f >> l1))
log_error("Line %u cannot be interpreted as an output!\n", line_count); log_error("Line %u cannot be interpreted as an output!\n", line_count);
log_debug2("%d is an output\n", l1); log_debug2("%d is an output\n", l1);
const unsigned variable = l1 >> 1; RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i));
const bool invert = l1 & 1;
RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
RTLIL::Wire *wire = module->wire(wire_name);
if (!wire)
wire = createWireIfNotExists(module, l1);
else if (wire->port_input || wire->port_output) {
RTLIL::Wire *new_wire = module->addWire(NEW_ID);
module->connect(new_wire, wire);
wire = new_wire;
}
wire->port_output = true; wire->port_output = true;
module->connect(wire, createWireIfNotExists(module, l1));
outputs.push_back(wire); outputs.push_back(wire);
} }
std::getline(f, line); // Ignore up to start of next line
// Parse bad properties // Parse bad properties
for (unsigned i = 0; i < B; ++i, ++line_count) { for (unsigned i = 0; i < B; ++i, ++line_count) {