mirror of https://github.com/YosysHQ/yosys.git
kernel: optimise Module::remove(const pool<RTLIL::Wire*>()
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@ -1586,30 +1586,25 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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const pool<RTLIL::Wire*> *wires_p;
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const pool<RTLIL::Wire*> *wires_p;
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void operator()(RTLIL::SigSpec &sig) {
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void operator()(RTLIL::SigSpec &sig) {
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std::vector<RTLIL::SigChunk> chunks = sig;
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for (auto &c : sig.chunks_)
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for (auto &c : chunks)
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if (c.wire != NULL && wires_p->count(c.wire)) {
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if (c.wire != NULL && wires_p->count(c.wire)) {
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c.wire = module->addWire(NEW_ID, c.width);
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c.wire = module->addWire(NEW_ID, c.width);
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c.offset = 0;
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c.offset = 0;
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}
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}
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sig = chunks;
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}
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}
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void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
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void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
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log_assert(GetSize(lhs) == GetSize(rhs));
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log_assert(GetSize(lhs) == GetSize(rhs));
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RTLIL::SigSpec new_lhs, new_rhs;
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lhs.unpack();
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rhs.unpack();
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for (int i = 0; i < GetSize(lhs); i++) {
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for (int i = 0; i < GetSize(lhs); i++) {
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RTLIL::SigBit lhs_bit = lhs[i];
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RTLIL::SigBit &lhs_bit = lhs.bits_[i];
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if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
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if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
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continue;
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continue;
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RTLIL::SigBit rhs_bit = rhs[i];
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RTLIL::SigBit &rhs_bit = rhs.bits_[i];
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if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
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if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
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continue;
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continue;
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new_lhs.append(lhs_bit);
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new_rhs.append(rhs_bit);
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}
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}
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lhs = new_lhs;
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rhs = new_rhs;
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}
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}
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};
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};
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@ -758,6 +758,10 @@ private:
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unpack();
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unpack();
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}
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}
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// Only used by Module::remove(const pool<Wire*> &wires)
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// but cannot be more specific as it isn't yet declared
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friend struct RTLIL::Module;
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public:
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public:
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SigSpec();
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SigSpec();
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SigSpec(const RTLIL::SigSpec &other);
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SigSpec(const RTLIL::SigSpec &other);
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