riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' of https://github.com/YosysHQ/yosys

This commit is contained in:
Pepijn de Vos 2019-09-04 10:37:27 +02:00
parent ec56438cf2 58af64b63a
commit b51c972296
3 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
backends/aiger/xaiger.cc
View File

@ -261,11 +261,12 @@ struct XAigerWriter
}
}
else {
bool cell_known = cell->known();
bool cell_known = inst_module || cell->known();
for (const auto &c : cell->connections()) {
if (c.second.is_fully_const()) continue;
auto is_input = !cell_known || cell->input(c.first);
auto is_output = !cell_known || cell->output(c.first);
auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
if (!is_input && !is_output)
log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));

2
tests/simple/run-test.sh
View File

@ -12,7 +12,7 @@ done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
if ! command -v iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi

2
tests/simple_abc9/run-test.sh
View File

@ -12,7 +12,7 @@ done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
if ! command -v iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi