riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #1228 from YosysHQ/dave/yy_buf_size 

verilog_lexer: Increase YY_BUF_SIZE to 65536
This commit is contained in:
Eddie Hung 2019-07-29 09:16:09 -07:00 committed by GitHub
parent ccf759864a 92694ea3a9
commit b4f38cca77
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
frontends/verilog/verilog_lexer.l
View File

@ -70,6 +70,9 @@ YOSYS_NAMESPACE_END
#define YY_INPUT(buf,result,max_size) \ #define YY_INPUT(buf,result,max_size) \
result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size) result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
#undef YY_BUF_SIZE
#define YY_BUF_SIZE 65536
%} %}
%option yylineno %option yylineno