From 11f330ed223f524cbbdbe2433599990a69b8f380 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 11:53:37 +0300 Subject: [PATCH 001/123] Add tests for ECP5 architecture --- Makefile | 1 + tests/ecp5/.gitignore | 2 + tests/ecp5/add_sub.v | 13 + tests/ecp5/add_sub.ys | 8 + tests/ecp5/adffs.v | 91 ++ tests/ecp5/adffs.ys | 10 + tests/ecp5/alu.v | 19 + tests/ecp5/alu.ys | 11 + tests/ecp5/counter.v | 17 + tests/ecp5/counter.ys | 11 + tests/ecp5/dffs.v | 37 + tests/ecp5/dffs.ys | 9 + tests/ecp5/div_mod.v | 13 + tests/ecp5/div_mod.ys | 12 + tests/ecp5/dpram.v | 23 + tests/ecp5/dpram.ys | 18 + tests/ecp5/dpram_synth.v | 165 +++ tests/ecp5/fsm.v | 73 ++ tests/ecp5/fsm.ys | 13 + tests/ecp5/latches.v | 58 + tests/ecp5/latches.ys | 17 + tests/ecp5/latches_synth.v | 109 ++ tests/ecp5/logic.v | 18 + tests/ecp5/logic.ys | 7 + tests/ecp5/macc.v | 25 + tests/ecp5/macc.ys | 15 + tests/ecp5/memory.v | 21 + tests/ecp5/memory.ys | 21 + tests/ecp5/memory_synth.v | 2121 ++++++++++++++++++++++++++++++++++++ tests/ecp5/mul.v | 11 + tests/ecp5/mul.ys | 11 + tests/ecp5/mux.v | 100 ++ tests/ecp5/mux.ys | 11 + tests/ecp5/rom.v | 18 + tests/ecp5/rom.ys | 9 + tests/ecp5/run-test.sh | 20 + tests/ecp5/shifter.v | 22 + tests/ecp5/shifter.ys | 9 + tests/ecp5/tribuf.v | 23 + tests/ecp5/tribuf.ys | 9 + 40 files changed, 3201 insertions(+) create mode 100644 tests/ecp5/.gitignore create mode 100644 tests/ecp5/add_sub.v create mode 100644 tests/ecp5/add_sub.ys create mode 100644 tests/ecp5/adffs.v create mode 100644 tests/ecp5/adffs.ys create mode 100644 tests/ecp5/alu.v create mode 100644 tests/ecp5/alu.ys create mode 100644 tests/ecp5/counter.v create mode 100644 tests/ecp5/counter.ys create mode 100644 tests/ecp5/dffs.v create mode 100644 tests/ecp5/dffs.ys create mode 100644 tests/ecp5/div_mod.v create mode 100644 tests/ecp5/div_mod.ys create mode 100644 tests/ecp5/dpram.v create mode 100644 tests/ecp5/dpram.ys create mode 100644 tests/ecp5/dpram_synth.v create mode 100644 tests/ecp5/fsm.v create mode 100644 tests/ecp5/fsm.ys create mode 100644 tests/ecp5/latches.v create mode 100644 tests/ecp5/latches.ys create mode 100644 tests/ecp5/latches_synth.v create mode 100644 tests/ecp5/logic.v create mode 100644 tests/ecp5/logic.ys create mode 100644 tests/ecp5/macc.v create mode 100644 tests/ecp5/macc.ys create mode 100644 tests/ecp5/memory.v create mode 100644 tests/ecp5/memory.ys create mode 100644 tests/ecp5/memory_synth.v create mode 100644 tests/ecp5/mul.v create mode 100644 tests/ecp5/mul.ys create mode 100644 tests/ecp5/mux.v create mode 100644 tests/ecp5/mux.ys create mode 100644 tests/ecp5/rom.v create mode 100644 tests/ecp5/rom.ys create mode 100755 tests/ecp5/run-test.sh create mode 100644 tests/ecp5/shifter.v create mode 100644 tests/ecp5/shifter.ys create mode 100644 tests/ecp5/tribuf.v create mode 100644 tests/ecp5/tribuf.ys diff --git a/Makefile b/Makefile index 2cac80f0f..d4f1d3d68 100644 --- a/Makefile +++ b/Makefile @@ -710,6 +710,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..7ec2b0114 --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,10 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:TRELLIS_FF +select -assert-count 7 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/alu.v b/tests/ecp5/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/ecp5/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/ecp5/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/ecp5/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys new file mode 100644 index 000000000..c65c21622 --- /dev/null +++ b/tests/ecp5/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..5510bb440 --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,9 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..fb13be5d5 --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 48 t:L6MUX21 +select -assert-count 194 t:LUT4 +select -assert-count 84 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/ecp5/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/ecp5/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D From 55fbc1a355a6139872a176318356ecdb71a35f5d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 12:11:12 +0300 Subject: [PATCH 002/123] Uncomment sat command in memory.ys test. --- tests/ecp5/memory.ys | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys index c90f1991e..9cc6bb5be 100644 --- a/tests/ecp5/memory.ys +++ b/tests/ecp5/memory.ys @@ -7,8 +7,7 @@ memory opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top From a203c8569cb6fc7093a5d09e4c64d8e545f81e39 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 4 Sep 2019 12:15:52 +0300 Subject: [PATCH 003/123] Fix ecp5 tests - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5; --- tests/ecp5/alu.ys | 12 +- tests/ecp5/counter.ys | 9 +- tests/ecp5/dpram.ys | 1 - tests/ecp5/dpram_synth.v | 165 --- tests/ecp5/fsm.ys | 15 +- tests/ecp5/latches.ys | 1 - tests/ecp5/latches_synth.v | 109 -- tests/ecp5/logic.ys | 6 +- tests/ecp5/memory.ys | 1 - tests/ecp5/memory_synth.v | 2121 ------------------------------------ tests/ecp5/shifter.ys | 7 +- 11 files changed, 26 insertions(+), 2421 deletions(-) delete mode 100644 tests/ecp5/dpram_synth.v delete mode 100644 tests/ecp5/latches_synth.v delete mode 100644 tests/ecp5/memory_synth.v diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys index bd859efc4..d10cd63b2 100644 --- a/tests/ecp5/alu.ys +++ b/tests/ecp5/alu.ys @@ -2,10 +2,12 @@ read_verilog alu.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D +select -assert-count 32 t:CCU2C +select -assert-count 253 t:L6MUX21 +select -assert-count 1150 t:LUT4 +select -assert-count 423 t:PFUMX +select -assert-count 32 t:TRELLIS_FF +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys index c65c21622..8ef70778f 100644 --- a/tests/ecp5/counter.ys +++ b/tests/ecp5/counter.ys @@ -2,10 +2,9 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:SB_CARRY -select -assert-count 8 t:SB_DFFR -select -assert-count 8 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D +select -assert-count 4 t:CCU2C +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys index b88eb80dd..786dee134 100644 --- a/tests/ecp5/dpram.ys +++ b/tests/ecp5/dpram.ys @@ -15,4 +15,3 @@ design -load postopt cd top select -assert-count 1 t:DP16KD select -assert-none t:DP16KD %% t:* %D -write_verilog dpram_synth.v diff --git a/tests/ecp5/dpram_synth.v b/tests/ecp5/dpram_synth.v deleted file mode 100644 index 7ae20bbba..000000000 --- a/tests/ecp5/dpram_synth.v +++ /dev/null @@ -1,165 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* dynports = 1 *) -(* top = 1 *) -(* src = "dpram.v:4" *) -module top(din, write_en, waddr, wclk, raddr, rclk, dout); - (* unused_bits = "8" *) - wire [8:0] _0_; - (* src = "dpram.v:8" *) - input [7:0] din; - (* src = "dpram.v:10" *) - output [7:0] dout; - (* src = "dpram.v:7" *) - input [7:0] raddr; - (* src = "dpram.v:9" *) - input rclk; - (* src = "dpram.v:7" *) - input [7:0] waddr; - (* src = "dpram.v:9" *) - input wclk; - (* src = "dpram.v:9" *) - input write_en; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/brams_map.v:79" *) - DP16KD #( - .CLKAMUX("CLKA"), - .CLKBMUX("CLKB"), - .DATA_WIDTH_A(32'sd9), - .DATA_WIDTH_B(32'sd9), - .GSR("DISABLED"), - .INITVAL_00(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_01(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_02(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_03(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_04(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_05(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_06(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_07(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_08(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_09(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_10(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_11(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_12(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_13(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_14(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_15(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_16(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_17(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_18(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_19(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_20(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_21(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_22(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_23(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_24(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_25(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_26(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_27(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_28(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_29(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_30(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_31(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_32(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_33(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_34(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_35(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_36(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_37(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_38(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_39(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .WRITEMODE_A("READBEFOREWRITE"), - .WRITEMODE_B("READBEFOREWRITE") - ) \mem.0.0.0 ( - .ADA0(1'h0), - .ADA1(1'h0), - .ADA10(waddr[7]), - .ADA11(1'h0), - .ADA12(1'h0), - .ADA13(1'h0), - .ADA2(1'h0), - .ADA3(waddr[0]), - .ADA4(waddr[1]), - .ADA5(waddr[2]), - .ADA6(waddr[3]), - .ADA7(waddr[4]), - .ADA8(waddr[5]), - .ADA9(waddr[6]), - .ADB0(1'h0), - .ADB1(1'h0), - .ADB10(raddr[7]), - .ADB11(1'h0), - .ADB12(1'h0), - .ADB13(1'h0), - .ADB2(1'h0), - .ADB3(raddr[0]), - .ADB4(raddr[1]), - .ADB5(raddr[2]), - .ADB6(raddr[3]), - .ADB7(raddr[4]), - .ADB8(raddr[5]), - .ADB9(raddr[6]), - .CEA(1'h1), - .CEB(1'h1), - .CLKA(wclk), - .CLKB(rclk), - .DIA0(din[0]), - .DIA1(din[1]), - .DIA10(1'h0), - .DIA11(1'h0), - .DIA12(1'h0), - .DIA13(1'h0), - .DIA14(1'h0), - .DIA15(1'h0), - .DIA16(1'h0), - .DIA17(1'h0), - .DIA2(din[2]), - .DIA3(din[3]), - .DIA4(din[4]), - .DIA5(din[5]), - .DIA6(din[6]), - .DIA7(din[7]), - .DIA8(1'h0), - .DIA9(1'h0), - .DOB0(dout[0]), - .DOB1(dout[1]), - .DOB2(dout[2]), - .DOB3(dout[3]), - .DOB4(dout[4]), - .DOB5(dout[5]), - .DOB6(dout[6]), - .DOB7(dout[7]), - .DOB8(_0_[8]), - .OCEA(1'h1), - .OCEB(1'h1), - .RSTA(1'h0), - .RSTB(1'h0), - .WEA(write_en), - .WEB(1'h0) - ); - assign _0_[7:0] = dout; -endmodule diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 4cc8629d6..bdd910163 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -2,12 +2,13 @@ read_verilog fsm.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - -select -assert-count 2 t:SB_DFFESR -select -assert-count 2 t:SB_DFFSR -select -assert-count 1 t:SB_DFFSS -select -assert-count 13 t:SB_LUT4 -select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D +select -assert-count 1 t:L6MUX21 +select -assert-count 15 t:LUT4 +select -assert-count 6 t:PFUMX +select -assert-count 6 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index 6eaf77cfd..b9d8faf87 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -14,4 +14,3 @@ cd top select -assert-count 4 t:LUT4 select -assert-count 1 t:PFUMX select -assert-none t:LUT4 t:PFUMX %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ecp5/latches_synth.v b/tests/ecp5/latches_synth.v deleted file mode 100644 index 816e10d4d..000000000 --- a/tests/ecp5/latches_synth.v +++ /dev/null @@ -1,109 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* top = 1 *) -(* src = "latches.v:27" *) -module top(clk, clr, pre, a, b, b1, b2); - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *) - wire _0_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *) - wire _1_; - (* src = "latches.v:31" *) - input a; - (* src = "latches.v:32" *) - output b; - (* src = "latches.v:32" *) - output b1; - (* src = "latches.v:32" *) - output b2; - (* src = "latches.v:28" *) - input clk; - (* src = "latches.v:29" *) - input clr; - (* src = "latches.v:30" *) - input pre; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.d ; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.en ; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.q ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.d ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.en ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.q ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.clr ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.d ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.en ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.pre ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.q ; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:106" *) - LUT4 #( - .INIT(16'h5150) - ) _2_ ( - .A(clr), - .B(clk), - .C(pre), - .D(b2), - .Z(_0_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:108" *) - LUT4 #( - .INIT(16'h5554) - ) _3_ ( - .A(clr), - .B(clk), - .C(pre), - .D(b2), - .Z(_1_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:110" *) - PFUMX _4_ ( - .ALUT(_1_), - .BLUT(_0_), - .C0(a), - .Z(b2) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x1x1x0x0x1x0x0) - ) _5_ ( - .A(1'h0), - .B(clk), - .C(b), - .D(a), - .Z(b) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x1x0x1x1x0x0x0) - ) _6_ ( - .A(1'h0), - .B(clk), - .C(b1), - .D(a), - .Z(b1) - ); - assign \u_latchn.d = a; - assign \u_latchn.en = clk; - assign \u_latchn.q = b1; - assign \u_latchp.d = a; - assign \u_latchp.en = clk; - assign \u_latchp.q = b; - assign \u_latchsr.clr = clr; - assign \u_latchsr.d = a; - assign \u_latchsr.en = clk; - assign \u_latchsr.pre = pre; - assign \u_latchsr.q = b2; -endmodule diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys index fc5e5b1d8..34125fea9 100644 --- a/tests/ecp5/logic.ys +++ b/tests/ecp5/logic.ys @@ -1,7 +1,7 @@ read_verilog logic.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 9 t:SB_LUT4 -select -assert-none t:SB_LUT4 %% t:* %D +select -assert-count 9 t:LUT4 +select -assert-none t:LUT4 %% t:* %D diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys index 9cc6bb5be..9b475f122 100644 --- a/tests/ecp5/memory.ys +++ b/tests/ecp5/memory.ys @@ -17,4 +17,3 @@ select -assert-count 32 t:PFUMX select -assert-count 8 t:TRELLIS_DPR16X4 select -assert-count 35 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ecp5/memory_synth.v b/tests/ecp5/memory_synth.v deleted file mode 100644 index a6172de61..000000000 --- a/tests/ecp5/memory_synth.v +++ /dev/null @@ -1,2121 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* top = 1 *) -(* src = "memory.v:1" *) -module top(data_a, addr_a, we_a, clk, q_a); - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _000_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _001_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _002_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _003_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _004_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _005_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _006_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _007_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _008_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _009_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _010_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _011_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _012_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _013_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _014_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _015_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _016_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _017_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _018_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _019_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _020_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _021_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _022_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _023_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _024_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _025_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _026_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _027_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _028_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _029_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _030_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _031_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _032_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _033_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _034_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _035_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _036_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _037_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _038_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _039_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _040_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _041_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _042_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _043_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _044_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _045_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _046_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _047_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _048_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _049_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _050_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _051_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _052_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _053_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _054_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _055_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _056_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _057_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _058_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _059_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _060_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _061_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _062_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _063_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _064_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _065_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _066_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _067_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _068_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _069_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _070_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _071_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _072_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _073_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _074_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _075_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _076_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _077_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _078_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _079_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _080_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _081_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _082_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _083_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _084_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _085_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _086_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _087_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _088_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _089_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _090_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _091_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _092_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _093_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _094_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _095_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _096_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _097_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _098_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _099_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _100_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _101_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _102_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _103_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _104_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _105_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _106_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _107_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _108_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _109_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _110_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _111_; - wire _112_; - wire _113_; - wire _114_; - wire _115_; - wire _116_; - wire _117_; - wire _118_; - wire _119_; - wire _120_; - wire _121_; - wire _122_; - wire _123_; - wire _124_; - wire _125_; - wire _126_; - wire _127_; - wire _128_; - wire _129_; - wire _130_; - wire _131_; - wire _132_; - wire _133_; - wire _134_; - wire _135_; - wire _136_; - wire _137_; - wire _138_; - wire _139_; - wire _140_; - wire _141_; - wire _142_; - wire _143_; - wire _144_; - wire _145_; - wire _146_; - wire _147_; - wire _148_; - wire _149_; - wire _150_; - wire _151_; - wire _152_; - wire _153_; - wire [3:0] _154_; - wire [3:0] _155_; - wire [3:0] _156_; - wire [3:0] _157_; - wire [3:0] _158_; - wire [3:0] _159_; - wire [3:0] _160_; - wire [3:0] _161_; - (* src = "memory.v:4" *) - input [6:1] addr_a; - (* src = "memory.v:5" *) - input clk; - (* src = "memory.v:3" *) - input [7:0] data_a; - (* src = "memory.v:6" *) - output [7:0] q_a; - (* src = "memory.v:5" *) - input we_a; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx0xxx1) - ) _162_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_147_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx1xxx0) - ) _163_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_148_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx1xxx0) - ) _164_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[6]), - .D(addr_a[5]), - .Z(_149_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x0x0x0x0x0x0x0) - ) _165_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_153_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x0x0x1x0) - ) _166_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x1x0x0x0) - ) _167_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x1x0x0x0) - ) _168_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[6]), - .D(addr_a[5]), - .Z(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _169_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_000_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _170_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_001_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _171_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_002_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _172_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_003_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _173_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_004_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _174_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_005_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _175_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_006_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _176_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_007_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _177_ ( - .ALUT(_001_), - .BLUT(_000_), - .C0(_132_), - .Z(_008_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _178_ ( - .ALUT(_003_), - .BLUT(_002_), - .C0(_132_), - .Z(_009_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _179_ ( - .ALUT(_005_), - .BLUT(_004_), - .C0(_132_), - .Z(_010_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _180_ ( - .ALUT(_007_), - .BLUT(_006_), - .C0(_132_), - .Z(_011_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _181_ ( - .D0(_008_), - .D1(_009_), - .SD(_128_), - .Z(_012_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _182_ ( - .D0(_010_), - .D1(_011_), - .SD(_128_), - .Z(_013_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _183_ ( - .D0(_012_), - .D1(_013_), - .SD(_140_), - .Z(q_a[4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _184_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_014_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _185_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_015_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _186_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_016_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _187_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_017_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _188_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_018_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _189_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_019_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _190_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_020_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _191_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_021_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _192_ ( - .ALUT(_015_), - .BLUT(_014_), - .C0(_133_), - .Z(_022_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _193_ ( - .ALUT(_017_), - .BLUT(_016_), - .C0(_133_), - .Z(_023_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _194_ ( - .ALUT(_019_), - .BLUT(_018_), - .C0(_133_), - .Z(_024_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _195_ ( - .ALUT(_021_), - .BLUT(_020_), - .C0(_133_), - .Z(_025_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _196_ ( - .D0(_022_), - .D1(_023_), - .SD(_129_), - .Z(_026_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _197_ ( - .D0(_024_), - .D1(_025_), - .SD(_129_), - .Z(_027_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _198_ ( - .D0(_026_), - .D1(_027_), - .SD(_141_), - .Z(q_a[5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _199_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_028_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _200_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_029_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _201_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_030_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _202_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_031_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _203_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_032_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _204_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_033_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _205_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_034_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _206_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_035_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _207_ ( - .ALUT(_029_), - .BLUT(_028_), - .C0(_134_), - .Z(_036_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _208_ ( - .ALUT(_031_), - .BLUT(_030_), - .C0(_134_), - .Z(_037_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _209_ ( - .ALUT(_033_), - .BLUT(_032_), - .C0(_134_), - .Z(_038_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _210_ ( - .ALUT(_035_), - .BLUT(_034_), - .C0(_134_), - .Z(_039_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _211_ ( - .D0(_036_), - .D1(_037_), - .SD(_130_), - .Z(_040_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _212_ ( - .D0(_038_), - .D1(_039_), - .SD(_130_), - .Z(_041_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _213_ ( - .D0(_040_), - .D1(_041_), - .SD(_142_), - .Z(q_a[6]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _214_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_042_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _215_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_043_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _216_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_044_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _217_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_045_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _218_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_046_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _219_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_047_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _220_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_048_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _221_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_049_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _222_ ( - .ALUT(_043_), - .BLUT(_042_), - .C0(_135_), - .Z(_050_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _223_ ( - .ALUT(_045_), - .BLUT(_044_), - .C0(_135_), - .Z(_051_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _224_ ( - .ALUT(_047_), - .BLUT(_046_), - .C0(_135_), - .Z(_052_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _225_ ( - .ALUT(_049_), - .BLUT(_048_), - .C0(_135_), - .Z(_053_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _226_ ( - .D0(_050_), - .D1(_051_), - .SD(_131_), - .Z(_054_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _227_ ( - .D0(_052_), - .D1(_053_), - .SD(_131_), - .Z(_055_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _228_ ( - .D0(_054_), - .D1(_055_), - .SD(_143_), - .Z(q_a[7]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _229_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_056_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _230_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_057_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _231_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_058_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _232_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_059_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _233_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_060_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _234_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_061_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _235_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_062_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _236_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_063_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _237_ ( - .ALUT(_057_), - .BLUT(_056_), - .C0(_116_), - .Z(_064_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _238_ ( - .ALUT(_059_), - .BLUT(_058_), - .C0(_116_), - .Z(_065_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _239_ ( - .ALUT(_061_), - .BLUT(_060_), - .C0(_116_), - .Z(_066_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _240_ ( - .ALUT(_063_), - .BLUT(_062_), - .C0(_116_), - .Z(_067_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _241_ ( - .D0(_064_), - .D1(_065_), - .SD(_112_), - .Z(_068_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _242_ ( - .D0(_066_), - .D1(_067_), - .SD(_112_), - .Z(_069_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _243_ ( - .D0(_068_), - .D1(_069_), - .SD(_124_), - .Z(q_a[0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _244_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_070_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _245_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_071_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _246_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_072_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _247_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_073_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _248_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_074_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _249_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_075_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _250_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_076_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _251_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_077_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _252_ ( - .ALUT(_071_), - .BLUT(_070_), - .C0(_117_), - .Z(_078_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _253_ ( - .ALUT(_073_), - .BLUT(_072_), - .C0(_117_), - .Z(_079_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _254_ ( - .ALUT(_075_), - .BLUT(_074_), - .C0(_117_), - .Z(_080_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _255_ ( - .ALUT(_077_), - .BLUT(_076_), - .C0(_117_), - .Z(_081_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _256_ ( - .D0(_078_), - .D1(_079_), - .SD(_113_), - .Z(_082_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _257_ ( - .D0(_080_), - .D1(_081_), - .SD(_113_), - .Z(_083_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _258_ ( - .D0(_082_), - .D1(_083_), - .SD(_125_), - .Z(q_a[1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _259_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_084_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _260_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_085_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _261_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_086_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _262_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_087_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _263_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_088_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _264_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_089_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _265_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_090_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _266_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_091_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _267_ ( - .ALUT(_085_), - .BLUT(_084_), - .C0(_118_), - .Z(_092_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _268_ ( - .ALUT(_087_), - .BLUT(_086_), - .C0(_118_), - .Z(_093_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _269_ ( - .ALUT(_089_), - .BLUT(_088_), - .C0(_118_), - .Z(_094_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _270_ ( - .ALUT(_091_), - .BLUT(_090_), - .C0(_118_), - .Z(_095_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _271_ ( - .D0(_092_), - .D1(_093_), - .SD(_114_), - .Z(_096_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _272_ ( - .D0(_094_), - .D1(_095_), - .SD(_114_), - .Z(_097_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _273_ ( - .D0(_096_), - .D1(_097_), - .SD(_126_), - .Z(q_a[2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _274_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_098_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _275_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_099_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _276_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_100_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _277_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_101_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _278_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_102_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _279_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_103_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _280_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_104_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _281_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_105_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _282_ ( - .ALUT(_099_), - .BLUT(_098_), - .C0(_119_), - .Z(_106_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _283_ ( - .ALUT(_101_), - .BLUT(_100_), - .C0(_119_), - .Z(_107_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _284_ ( - .ALUT(_103_), - .BLUT(_102_), - .C0(_119_), - .Z(_108_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _285_ ( - .ALUT(_105_), - .BLUT(_104_), - .C0(_119_), - .Z(_109_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _286_ ( - .D0(_106_), - .D1(_107_), - .SD(_115_), - .Z(_110_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _287_ ( - .D0(_108_), - .D1(_109_), - .SD(_115_), - .Z(_111_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _288_ ( - .D0(_110_), - .D1(_111_), - .SD(_127_), - .Z(q_a[3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _289_ ( - .CLK(clk), - .DI(_147_), - .LSR(1'h0), - .Q(_144_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _290_ ( - .CLK(clk), - .DI(_154_[0]), - .LSR(1'h0), - .Q(_112_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _291_ ( - .CLK(clk), - .DI(_154_[1]), - .LSR(1'h0), - .Q(_113_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _292_ ( - .CLK(clk), - .DI(_154_[2]), - .LSR(1'h0), - .Q(_114_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _293_ ( - .CLK(clk), - .DI(_154_[3]), - .LSR(1'h0), - .Q(_115_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _294_ ( - .CLK(clk), - .DI(_155_[0]), - .LSR(1'h0), - .Q(_116_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _295_ ( - .CLK(clk), - .DI(_155_[1]), - .LSR(1'h0), - .Q(_117_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _296_ ( - .CLK(clk), - .DI(_155_[2]), - .LSR(1'h0), - .Q(_118_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _297_ ( - .CLK(clk), - .DI(_155_[3]), - .LSR(1'h0), - .Q(_119_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _298_ ( - .CLK(clk), - .DI(_156_[0]), - .LSR(1'h0), - .Q(_120_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _299_ ( - .CLK(clk), - .DI(_156_[1]), - .LSR(1'h0), - .Q(_121_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _300_ ( - .CLK(clk), - .DI(_156_[2]), - .LSR(1'h0), - .Q(_122_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _301_ ( - .CLK(clk), - .DI(_156_[3]), - .LSR(1'h0), - .Q(_123_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _302_ ( - .CLK(clk), - .DI(_149_), - .LSR(1'h0), - .Q(_146_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _303_ ( - .CLK(clk), - .DI(_157_[0]), - .LSR(1'h0), - .Q(_124_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _304_ ( - .CLK(clk), - .DI(_157_[1]), - .LSR(1'h0), - .Q(_125_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _305_ ( - .CLK(clk), - .DI(_157_[2]), - .LSR(1'h0), - .Q(_126_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _306_ ( - .CLK(clk), - .DI(_157_[3]), - .LSR(1'h0), - .Q(_127_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _307_ ( - .CLK(clk), - .DI(_158_[0]), - .LSR(1'h0), - .Q(_128_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _308_ ( - .CLK(clk), - .DI(_158_[1]), - .LSR(1'h0), - .Q(_129_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _309_ ( - .CLK(clk), - .DI(_158_[2]), - .LSR(1'h0), - .Q(_130_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _310_ ( - .CLK(clk), - .DI(_158_[3]), - .LSR(1'h0), - .Q(_131_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _311_ ( - .CLK(clk), - .DI(_159_[0]), - .LSR(1'h0), - .Q(_132_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _312_ ( - .CLK(clk), - .DI(_159_[1]), - .LSR(1'h0), - .Q(_133_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _313_ ( - .CLK(clk), - .DI(_159_[2]), - .LSR(1'h0), - .Q(_134_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _314_ ( - .CLK(clk), - .DI(_159_[3]), - .LSR(1'h0), - .Q(_135_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _315_ ( - .CLK(clk), - .DI(_148_), - .LSR(1'h0), - .Q(_145_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _316_ ( - .CLK(clk), - .DI(_160_[0]), - .LSR(1'h0), - .Q(_136_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _317_ ( - .CLK(clk), - .DI(_160_[1]), - .LSR(1'h0), - .Q(_137_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _318_ ( - .CLK(clk), - .DI(_160_[2]), - .LSR(1'h0), - .Q(_138_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _319_ ( - .CLK(clk), - .DI(_160_[3]), - .LSR(1'h0), - .Q(_139_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _320_ ( - .CLK(clk), - .DI(_161_[0]), - .LSR(1'h0), - .Q(_140_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _321_ ( - .CLK(clk), - .DI(_161_[1]), - .LSR(1'h0), - .Q(_141_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _322_ ( - .CLK(clk), - .DI(_161_[2]), - .LSR(1'h0), - .Q(_142_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _323_ ( - .CLK(clk), - .DI(_161_[3]), - .LSR(1'h0), - .Q(_143_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.0.0 ( - .DI(data_a[3:0]), - .DO(_154_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.1.0 ( - .DI(data_a[3:0]), - .DO(_155_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.2.0 ( - .DI(data_a[3:0]), - .DO(_156_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.3.0 ( - .DI(data_a[3:0]), - .DO(_157_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_153_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.0.0 ( - .DI(data_a[7:4]), - .DO(_158_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.1.0 ( - .DI(data_a[7:4]), - .DO(_159_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.2.0 ( - .DI(data_a[7:4]), - .DO(_160_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.3.0 ( - .DI(data_a[7:4]), - .DO(_161_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_153_) - ); -endmodule diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys index 47d95d298..70fe6c45c 100644 --- a/tests/ecp5/shifter.ys +++ b/tests/ecp5/shifter.ys @@ -2,8 +2,9 @@ read_verilog shifter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:SB_DFF -select -assert-none t:SB_DFF %% t:* %D +stat +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D From 93f305b1c53ce49338bf276a7fb9c3aa4d578c9e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 4 Sep 2019 14:57:45 +0300 Subject: [PATCH 004/123] Remove stat command form shifter.ys test --- tests/ecp5/shifter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys index 70fe6c45c..e1901e1a8 100644 --- a/tests/ecp5/shifter.ys +++ b/tests/ecp5/shifter.ys @@ -5,6 +5,6 @@ flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -stat + select -assert-count 8 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D From c597c2f2ae10111b2dc28e9738ea336d8ad22b31 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 17 Sep 2019 12:19:31 +0300 Subject: [PATCH 005/123] adffs test update (equiv_opt -multiclock). div_mod test fix --- tests/ecp5/adffs.v | 18 +++++++----------- tests/ecp5/adffs.ys | 5 ++--- tests/ecp5/div_mod.ys | 6 +++--- 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/ecp5/adffs.v +++ b/tests/ecp5/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index 7ec2b0114..fc1363a32 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,10 +1,9 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 4 t:TRELLIS_FF -select -assert-count 7 t:LUT4 +select -assert-count 3 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys index fb13be5d5..9efb00701 100644 --- a/tests/ecp5/div_mod.ys +++ b/tests/ecp5/div_mod.ys @@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 28 t:CCU2C -select -assert-count 48 t:L6MUX21 -select -assert-count 194 t:LUT4 -select -assert-count 84 t:PFUMX +select -assert-count 26 t:L6MUX21 +select -assert-count 138 t:LUT4 +select -assert-count 60 t:PFUMX select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D From 5eb91fa69fc62482d09c1927b3a6f8164dee9408 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 18 Sep 2019 12:16:04 +0300 Subject: [PATCH 006/123] Add comment to dpram test about related issue. --- tests/ecp5/dpram.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys index 786dee134..3bc6bc1d0 100644 --- a/tests/ecp5/dpram.ys +++ b/tests/ecp5/dpram.ys @@ -8,6 +8,7 @@ opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter +#Blocked by issue #1358 (Missing ECP5 simulation models) #ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database. #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter From 27377c46634263beb5f8c28cb34b0c87ed6e9525 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 23 Sep 2019 12:12:02 +0300 Subject: [PATCH 007/123] Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. --- Makefile | 1 + tests/anlogic/.gitignore | 4 ++ tests/anlogic/add_sub.v | 13 +++++ tests/anlogic/add_sub.ys | 9 ++++ tests/anlogic/alu.v | 19 ++++++++ tests/anlogic/alu.ys | 17 +++++++ tests/anlogic/counter.v | 17 +++++++ tests/anlogic/counter.ys | 11 +++++ tests/anlogic/dffs.v | 37 ++++++++++++++ tests/anlogic/dffs.ys | 10 ++++ tests/anlogic/fsm.v | 73 ++++++++++++++++++++++++++++ tests/anlogic/fsm.ys | 14 ++++++ tests/anlogic/latches.v | 58 ++++++++++++++++++++++ tests/anlogic/latches.ys | 16 ++++++ tests/anlogic/memory.v | 21 ++++++++ tests/anlogic/memory.ys | 21 ++++++++ tests/anlogic/mux.v | 100 ++++++++++++++++++++++++++++++++++++++ tests/anlogic/mux.ys | 12 +++++ tests/anlogic/run-test.sh | 20 ++++++++ tests/anlogic/shifter.v | 22 +++++++++ tests/anlogic/shifter.ys | 9 ++++ tests/anlogic/tribuf.v | 23 +++++++++ tests/anlogic/tribuf.ys | 9 ++++ 23 files changed, 536 insertions(+) create mode 100644 tests/anlogic/.gitignore create mode 100644 tests/anlogic/add_sub.v create mode 100644 tests/anlogic/add_sub.ys create mode 100644 tests/anlogic/alu.v create mode 100644 tests/anlogic/alu.ys create mode 100644 tests/anlogic/counter.v create mode 100644 tests/anlogic/counter.ys create mode 100644 tests/anlogic/dffs.v create mode 100644 tests/anlogic/dffs.ys create mode 100644 tests/anlogic/fsm.v create mode 100644 tests/anlogic/fsm.ys create mode 100644 tests/anlogic/latches.v create mode 100644 tests/anlogic/latches.ys create mode 100644 tests/anlogic/memory.v create mode 100644 tests/anlogic/memory.ys create mode 100644 tests/anlogic/mux.v create mode 100644 tests/anlogic/mux.ys create mode 100755 tests/anlogic/run-test.sh create mode 100644 tests/anlogic/shifter.v create mode 100644 tests/anlogic/shifter.ys create mode 100644 tests/anlogic/tribuf.v create mode 100644 tests/anlogic/tribuf.ys diff --git a/Makefile b/Makefile index 2cac80f0f..742692f0d 100644 --- a/Makefile +++ b/Makefile @@ -710,6 +710,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/anlogic && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/anlogic/.gitignore b/tests/anlogic/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/anlogic/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/anlogic/add_sub.v b/tests/anlogic/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/anlogic/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys new file mode 100644 index 000000000..55c090506 --- /dev/null +++ b/tests/anlogic/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:AL_MAP_ADDER +select -assert-count 4 t:AL_MAP_LUT1 +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D + diff --git a/tests/anlogic/alu.v b/tests/anlogic/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/anlogic/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/anlogic/alu.ys b/tests/anlogic/alu.ys new file mode 100644 index 000000000..532ce82d5 --- /dev/null +++ b/tests/anlogic/alu.ys @@ -0,0 +1,17 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 66 t:AL_MAP_ADDER +select -assert-count 32 t:AL_MAP_LUT1 +select -assert-count 23 t:AL_MAP_LUT2 +select -assert-count 61 t:AL_MAP_LUT3 +select -assert-count 209 t:AL_MAP_LUT4 +select -assert-count 100 t:AL_MAP_LUT5 +select -assert-count 79 t:AL_MAP_LUT6 +select -assert-count 32 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/counter.v b/tests/anlogic/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/anlogic/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys new file mode 100644 index 000000000..5210221e3 --- /dev/null +++ b/tests/anlogic/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:AL_MAP_ADDER +select -assert-count 8 t:AL_MAP_SEQ +select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/anlogic/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys new file mode 100644 index 000000000..a15c6f24e --- /dev/null +++ b/tests/anlogic/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 2 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/anlogic/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys new file mode 100644 index 000000000..6eb7b9a71 --- /dev/null +++ b/tests/anlogic/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT2 +select -assert-count 5 t:AL_MAP_LUT5 +select -assert-count 1 t:AL_MAP_LUT6 +select -assert-count 6 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/anlogic/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys new file mode 100644 index 000000000..b5e52cf16 --- /dev/null +++ b/tests/anlogic/latches.ys @@ -0,0 +1,16 @@ +read_verilog latches.v +design -save read + +proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock +flatten +synth_anlogic +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read +synth_anlogic +cd top +select -assert-count 2 t:AL_MAP_LUT3 +select -assert-count 1 t:AL_MAP_LUT5 +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D diff --git a/tests/anlogic/memory.v b/tests/anlogic/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/anlogic/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/anlogic/memory.ys b/tests/anlogic/memory.ys new file mode 100644 index 000000000..8c0ce844e --- /dev/null +++ b/tests/anlogic/memory.ys @@ -0,0 +1,21 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top + +select -assert-count 8 t:AL_MAP_LUT2 +select -assert-count 8 t:AL_MAP_LUT4 +select -assert-count 8 t:AL_MAP_LUT5 +select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/anlogic/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys new file mode 100644 index 000000000..84a8bcccf --- /dev/null +++ b/tests/anlogic/mux.ys @@ -0,0 +1,12 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 4 t:AL_MAP_LUT4 +select -assert-count 4 t:AL_MAP_LUT5 +select -assert-count 1 t:AL_MAP_LUT6 +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D diff --git a/tests/anlogic/run-test.sh b/tests/anlogic/run-test.sh new file mode 100755 index 000000000..2c72ca3a9 --- /dev/null +++ b/tests/anlogic/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/anlogic/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys new file mode 100644 index 000000000..edd89b344 --- /dev/null +++ b/tests/anlogic/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/anlogic/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys new file mode 100644 index 000000000..663e93fb2 --- /dev/null +++ b/tests/anlogic/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D From eeb86247c59f7ea7f98c05eaa456d0ebe041d149 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 15:14:41 -0700 Subject: [PATCH 008/123] Update fsm.ys resource count --- tests/ecp5/fsm.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index bdd910163..36b10c0ce 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -8,7 +8,7 @@ equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 -select -assert-count 15 t:LUT4 -select -assert-count 6 t:PFUMX -select -assert-count 6 t:TRELLIS_FF +select -assert-count 13 t:LUT4 +select -assert-count 5 t:PFUMX +select -assert-count 5 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D From d992858318c9fae869a7d0d4ed046ed8c5ea5811 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 15:15:14 -0700 Subject: [PATCH 009/123] Move $x to end as per 7f0eec8 --- tests/ecp5/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/ecp5/run-test.sh +++ b/tests/ecp5/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then From f8d5e11aa7285fc92832b87063d530afe27eca28 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:54:04 -0700 Subject: [PATCH 010/123] Update resource count for alu.ys --- tests/ecp5/alu.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys index d10cd63b2..c2950b164 100644 --- a/tests/ecp5/alu.ys +++ b/tests/ecp5/alu.ys @@ -6,8 +6,8 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 32 t:CCU2C -select -assert-count 253 t:L6MUX21 -select -assert-count 1150 t:LUT4 -select -assert-count 423 t:PFUMX +select -assert-count 242 t:L6MUX21 +select -assert-count 1127 t:LUT4 +select -assert-count 417 t:PFUMX select -assert-count 32 t:TRELLIS_FF select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D From 1caaf5149258ff84ac2a6532c26e9ffb076183a9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:54:59 -0700 Subject: [PATCH 011/123] equiv_opt with -assert --- tests/ecp5/fsm.ys | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 36b10c0ce..6368edc57 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -2,9 +2,7 @@ read_verilog fsm.v hierarchy -top top proc flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 From fc56459746fec7751735749e3328378e1089b914 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Tue, 1 Oct 2019 10:55:34 +0300 Subject: [PATCH 012/123] run-test.sh Move $x at end of line. --- tests/anlogic/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/anlogic/run-test.sh b/tests/anlogic/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/anlogic/run-test.sh +++ b/tests/anlogic/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then From c28d4b804720c2cf0086e921748219150e9631b5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 14:52:40 -0700 Subject: [PATCH 013/123] Add test that is expecting to fail --- tests/sat/initval.ys | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..1627a37e3 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,3 +2,23 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts + +read_verilog < Date: Wed, 2 Oct 2019 16:08:46 -0700 Subject: [PATCH 014/123] Be mindful that sigmap(wire) could have dupes when checking \init --- passes/sat/sat.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 430bba1e8..93a4f225e 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -265,15 +265,18 @@ struct SatHelper RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); log_assert(lhs.size() == rhs.size()); + dict seen_init; RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); i--; } + else + seen_init[bit] = rhs[i]; } if (removed_bits.size()) From e730a595eeee1d9936a892c2477c99593d64bcfe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 17:48:55 -0700 Subject: [PATCH 015/123] Add test --- tests/various/peepopt.ys | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 6bca62e2b..dc0acf3ca 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -173,3 +173,34 @@ select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 2 t:$mux select -assert-count 2 t:$mux r:WIDTH=2 %i select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog < Date: Wed, 2 Oct 2019 17:53:42 -0700 Subject: [PATCH 016/123] Refactor peepopt_dffmux and be sensitive to \init when trimming --- passes/pmgen/peepopt_dffmux.pmg | 95 ++++++++++++++++++++++----------- 1 file changed, 63 insertions(+), 32 deletions(-) diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index c88a52226..2ec504cb4 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -8,21 +8,23 @@ match dff select GetSize(port(dff, \D)) > 1 endmatch +code sigD + sigD = port(dff, \D); +endcode + match rstmux select rstmux->type == $mux select GetSize(port(rstmux, \Y)) > 1 - index port(rstmux, \Y) === port(dff, \D) + index port(rstmux, \Y) === sigD choice BA {\B, \A} select port(rstmux, BA).is_fully_const() set rstmuxBA BA - optional + semioptional endmatch code sigD if (rstmux) sigD = port(rstmux, rstmuxBA == \B ? \A : \B); - else - sigD = port(dff, \D); endcode match cemux @@ -32,45 +34,70 @@ match cemux choice AB {\A, \B} index port(cemux, AB) === port(dff, \Q) set cemuxAB AB + semioptional endmatch code - SigSpec D = port(cemux, cemuxAB == \A ? \B : \A); - SigSpec Q = port(dff, \Q); + if (!cemux && !rstmux) + reject; +endcode + +code Const rst; - if (rstmux) + SigSpec D; + if (cemux) { + D = port(cemux, cemuxAB == \A ? \B : \A); + if (rstmux) + rst = port(rstmux, rstmuxBA).as_const(); + else + rst = Const(State::Sx, GetSize(D)); + } + else { + log_assert(rstmux); + D = port(rstmux, rstmuxBA == \B ? \A : \B); rst = port(rstmux, rstmuxBA).as_const(); + } + SigSpec Q = port(dff, \Q); int width = GetSize(D); - SigSpec &ceA = cemux->connections_.at(\A); - SigSpec &ceB = cemux->connections_.at(\B); - SigSpec &ceY = cemux->connections_.at(\Y); SigSpec &dffD = dff->connections_.at(\D); SigSpec &dffQ = dff->connections_.at(\Q); + Const init; + for (const auto &b : Q) { + auto it = b.wire->attributes.find(\init); + init.bits.push_back(it == b.wire->attributes.end() ? State::Sx : it->second[b.offset]); + } - if (D[width-1] == D[width-2]) { + auto cmpx = [=](State lhs, State rhs) { + if (lhs == State::Sx || rhs == State::Sx) + return true; + return lhs == rhs; + }; + + int i = width; + while (i > 2) { + i--; + if (D[i] != D[i-1]) + break; + if (!cmpx(rst[i], rst[i-1])) + break; + if (!cmpx(init[i], init[i-1])) + break; + if (!cmpx(rst[i], init[i])) + break; + module->connect(Q[i], Q[i-1]); did_something = true; - - SigBit sign = D[width-1]; - bool is_signed = sign.wire; - int i; - for (i = width-1; i >= 2; i--) { - if (!is_signed) { - module->connect(Q[i], sign); - if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1])) - break; - } - else { - module->connect(Q[i], Q[i-1]); - if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1])) - break; - } + } + if (i < width-1) { + if (cemux) { + SigSpec &ceA = cemux->connections_.at(\A); + SigSpec &ceB = cemux->connections_.at(\B); + SigSpec &ceY = cemux->connections_.at(\Y); + ceA.remove(i, width-i); + ceB.remove(i, width-i); + ceY.remove(i, width-i); + cemux->fixup_parameters(); } - - ceA.remove(i, width-i); - ceB.remove(i, width-i); - ceY.remove(i, width-i); - cemux->fixup_parameters(); dffD.remove(i, width-i); dffQ.remove(i, width-i); dff->fixup_parameters(); @@ -78,7 +105,11 @@ code log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i); accept; } - else { + else if (cemux) { + SigSpec &ceA = cemux->connections_.at(\A); + SigSpec &ceB = cemux->connections_.at(\B); + SigSpec &ceY = cemux->connections_.at(\Y); + int count = 0; for (int i = width-1; i >= 0; i--) { if (D[i].wire) From f6fabc8fda1eb00b0227f1a91d85b837a0609728 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 18:03:45 -0700 Subject: [PATCH 017/123] Update test --- tests/various/peepopt.ys | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index dc0acf3ca..734a22408 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -188,19 +188,9 @@ endmodule EOT proc -#equiv_opt -assert peepopt - -design -save gold -peepopt -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -seq 1 -verify -prove-asserts -show-ports miter - +equiv_opt -assert peepopt design -load postopt -wreduce -select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$dff r:WIDTH=4 %i select -assert-count 2 t:$mux -select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 2 t:$mux r:WIDTH=4 %i select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D From e4bd5aaebf7e329236b10c93eac9ad113231f00e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 18:12:25 -0700 Subject: [PATCH 018/123] Fix test --- tests/various/peepopt.ys | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 734a22408..1f18f1c74 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -188,8 +188,18 @@ endmodule EOT proc -equiv_opt -assert peepopt -design -load postopt +#equiv_opt -assert peepopt + +design -save gold +peepopt +wreduce +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 1 -verify -prove-asserts -show-ports miter + +design -load gate select -assert-count 1 t:$dff r:WIDTH=4 %i select -assert-count 2 t:$mux select -assert-count 2 t:$mux r:WIDTH=4 %i From e9645c7fa7fc349afad103ff8736699bb4dc0412 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 21:26:26 -0700 Subject: [PATCH 019/123] Fix broken CI, check reset even for constants, trim rstmux --- passes/pmgen/peepopt_dffmux.pmg | 51 +++++++++++++++++---------------- tests/various/peepopt.ys | 4 +-- 2 files changed, 29 insertions(+), 26 deletions(-) diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index 2ec504cb4..bfd155c58 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -74,9 +74,9 @@ code return lhs == rhs; }; - int i = width; - while (i > 2) { - i--; + int i = width-1; + while (i > 1) { + log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]); if (D[i] != D[i-1]) break; if (!cmpx(rst[i], rst[i-1])) @@ -86,26 +86,36 @@ code if (!cmpx(rst[i], init[i])) break; module->connect(Q[i], Q[i-1]); - did_something = true; + i--; } if (i < width-1) { + did_something = true; if (cemux) { SigSpec &ceA = cemux->connections_.at(\A); SigSpec &ceB = cemux->connections_.at(\B); SigSpec &ceY = cemux->connections_.at(\Y); - ceA.remove(i, width-i); - ceB.remove(i, width-i); - ceY.remove(i, width-i); + ceA.remove(i, width-1-i); + ceB.remove(i, width-1-i); + ceY.remove(i, width-1-i); cemux->fixup_parameters(); } - dffD.remove(i, width-i); - dffQ.remove(i, width-i); + if (rstmux) { + SigSpec &rstA = rstmux->connections_.at(\A); + SigSpec &rstB = rstmux->connections_.at(\B); + SigSpec &rstY = rstmux->connections_.at(\Y); + rstA.remove(i, width-1-i); + rstB.remove(i, width-1-i); + rstY.remove(i, width-1-i); + rstmux->fixup_parameters(); + } + dffD.remove(i, width-1-i); + dffQ.remove(i, width-1-i); dff->fixup_parameters(); - log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i); - accept; + log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux, "n/a"), log_id(rstmux, "n/a"), width-1-i); + width = i+1; } - else if (cemux) { + if (cemux) { SigSpec &ceA = cemux->connections_.at(\A); SigSpec &ceB = cemux->connections_.at(\B); SigSpec &ceY = cemux->connections_.at(\Y); @@ -114,15 +124,7 @@ code for (int i = width-1; i >= 0; i--) { if (D[i].wire) continue; - Wire *w = Q[i].wire; - auto it = w->attributes.find(\init); - State init; - if (it != w->attributes.end()) - init = it->second[Q[i].offset]; - else - init = State::Sx; - - if (init == State::Sx || init == D[i].data) { + if (cmpx(rst[i], D[i].data) && cmpx(init[i], D[i].data)) { count++; module->connect(Q[i], D[i]); ceA.remove(i); @@ -136,9 +138,10 @@ code did_something = true; cemux->fixup_parameters(); dff->fixup_parameters(); - log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count); + log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), log_id(rstmux, "n/a"), count); } - - accept; } + + if (did_something) + accept; endcode diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 1f18f1c74..4b130578b 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -131,8 +131,8 @@ EOT proc equiv_opt -assert peepopt design -load postopt -select -assert-count 1 t:$dff r:WIDTH=5 %i -select -assert-count 1 t:$mux r:WIDTH=5 %i +select -assert-count 1 t:$dff r:WIDTH=4 %i +select -assert-count 1 t:$mux r:WIDTH=4 %i select -assert-count 0 t:$dff t:$mux %% t:* %D #################### From f6b5e47e40b4a2bda6e5d928480ea218a6a911c2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 20:43:13 +0100 Subject: [PATCH 020/123] sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah --- frontends/ast/ast.cc | 3 ++ frontends/ast/ast.h | 7 ++-- frontends/ast/genrtlil.cc | 1 + frontends/ast/simplify.cc | 51 +++++++++++++++++++++++++++--- frontends/verilog/verilog_parser.y | 38 +++++++++++++++++++--- tests/svtypes/typedef1.sv | 22 +++++++++++++ 6 files changed, 111 insertions(+), 11 deletions(-) create mode 100644 tests/svtypes/typedef1.sv diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 21279cbfa..937dad9be 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -164,6 +164,8 @@ std::string AST::type2str(AstNodeType type) X(AST_MODPORT) X(AST_MODPORTMEMBER) X(AST_PACKAGE) + X(AST_WIRETYPE) + X(AST_TYPEDEF) #undef X default: log_abort(); @@ -206,6 +208,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch was_checked = false; range_valid = false; range_swapped = false; + is_custom_type = false; port_id = 0; range_left = -1; range_right = 0; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 93fee913e..fcc661b4c 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -148,7 +148,10 @@ namespace AST AST_INTERFACEPORTTYPE, AST_MODPORT, AST_MODPORTMEMBER, - AST_PACKAGE + AST_PACKAGE, + + AST_WIRETYPE, + AST_TYPEDEF }; // convert an node type to a string (e.g. for debug output) @@ -174,7 +177,7 @@ namespace AST // node content - most of it is unused in most node types std::string str; std::vector bits; - bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized; + bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized, is_custom_type; int port_id, range_left, range_right; uint32_t integer; double realvalue; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 407a34472..94f5c0a04 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -863,6 +863,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_PACKAGE: case AST_MODPORT: case AST_MODPORTMEMBER: + case AST_TYPEDEF: break; case AST_INTERFACEPORT: { // If a port in a module with unknown type is found, mark it with the attribute 'is_interface' diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index b1ee22f42..b94662bcd 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -318,7 +318,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } // activate const folding if this is anything that must be evaluated statically (ranges, parameters, attributes, etc.) - if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX) + if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX || type == AST_TYPEDEF) const_fold = true; if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM)) const_fold = true; @@ -336,6 +336,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, std::map this_wire_scope; for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; + if (node->type == AST_WIRE) { if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { for (auto c : node->children[0]->children) { @@ -405,14 +406,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, this_wire_scope[node->str] = node; } if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_GENVAR || - node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_DPI_FUNCTION || node->type == AST_CELL) { + node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_DPI_FUNCTION || node->type == AST_CELL || + node->type == AST_TYPEDEF) { backup_scope[node->str] = current_scope[node->str]; current_scope[node->str] = node; } } for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; - if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY) + if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF) while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM)) did_something = true; } @@ -780,6 +782,44 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, delete_children(); } + // resolve typedefs + if (type == AST_TYPEDEF) { + log_assert(children.size() == 1); + log_assert(children[0]->type == AST_WIRE); + while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + log_assert(!children[0]->is_custom_type); + } + + // resolve types of wires and parameters + if (type == AST_WIRE || type == AST_LOCALPARAM || type == AST_PARAMETER) { + if (is_custom_type) { + log_assert(children.size() == 1); + log_assert(children[0]->type == AST_WIRETYPE); + if (!current_scope.count(children[0]->str)) + log_file_error(filename, linenum, "Unknown identifier `%s' used as type name", children[0]->str.c_str()); + AstNode *resolved_type = current_scope.at(children[0]->str); + if (resolved_type->type != AST_TYPEDEF) + log_file_error(filename, linenum, "`%s' does not name a type", children[0]->str.c_str()); + log_assert(resolved_type->children.size() == 1); + AstNode *templ = resolved_type->children[0]; + delete_children(); // type reference no longer needed + + is_reg = templ->is_reg; + is_logic = templ->is_logic; + is_signed = templ->is_signed; + is_string = templ->is_string; + is_custom_type = templ->is_custom_type; + + range_valid = templ->range_valid; + range_swapped = templ->range_swapped; + range_left = templ->range_left; + range_right = templ->range_right; + for (auto template_child : templ->children) + children.push_back(template_child->clone()); + } + log_assert(!is_custom_type); + } + // resolve constant prefixes if (type == AST_PREFIX) { if (children[0]->type != AST_CONSTANT) { @@ -1194,7 +1234,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_BLOCK && str.empty()) { for (size_t i = 0; i < children.size(); i++) - if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM) + if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) log_file_error(children[i]->filename, children[i]->linenum, "Local declaration in unnamed block is an unsupported SystemVerilog feature!\n"); } @@ -1206,7 +1246,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, std::vector new_children; for (size_t i = 0; i < children.size(); i++) - if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM) { + if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) { children[i]->simplify(false, false, false, stage, -1, false, false); current_ast_mod->children.push_back(children[i]); current_scope[children[i]->str] = children[i]; @@ -2945,6 +2985,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma child->expand_genblock(index_var, prefix, name_map); } + if (backup_name_map.size() > 0) name_map.swap(backup_name_map); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4afd72b73..eb091bea6 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -112,6 +112,8 @@ struct specify_rise_fall { %define api.prefix {frontend_verilog_yy} +%glr-parser + /* The union is defined in the header, so we need to provide all the * includes it requires */ @@ -180,7 +182,7 @@ struct specify_rise_fall { %right UNARY_OPS %define parse.error verbose -%define parse.lac full +// %define parse.lac full %nonassoc FAKE_THEN %nonassoc TOK_ELSE @@ -206,6 +208,7 @@ design: task_func_decl design | param_decl design | localparam_decl design | + typedef_decl design | package design | interface design | /* empty */; @@ -426,6 +429,7 @@ package_body: package_body package_body_stmt |; package_body_stmt: + typedef_decl | localparam_decl; interface: @@ -452,7 +456,7 @@ interface_body: interface_body interface_body_stmt |; interface_body_stmt: - param_decl | localparam_decl | defparam_decl | wire_decl | always_stmt | assign_stmt | + param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt | modport_stmt; non_opt_delay: @@ -529,6 +533,11 @@ wire_type_token: } | TOK_CONST { current_wire_const = true; + } | + hierarchical_id { + astbuf3->is_custom_type = true; + astbuf3->children.push_back(new AstNode(AST_WIRETYPE)); + astbuf3->children.back()->str = *$1; }; non_opt_range: @@ -591,7 +600,7 @@ module_body: /* empty */; module_body_stmt: - task_func_decl | specify_block |param_decl | localparam_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | + task_func_decl | specify_block |param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block; checker_decl: @@ -1377,6 +1386,27 @@ assign_expr: ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3)); }; +typedef_decl: + TOK_TYPEDEF wire_type range TOK_ID ';' { + astbuf1 = $2; + astbuf2 = $3; + if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { + if (astbuf2) { + frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions."); + } else { + astbuf2 = new AstNode(AST_RANGE); + astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true)); + astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true)); + } + } + if (astbuf2 && astbuf2->children.size() != 2) + frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [:], [+:], or [-:]"); + if (astbuf2) + astbuf1->children.push_back(astbuf2); + ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1)); + ast_stack.back()->children.back()->str = *$4; + }; + cell_stmt: attr TOK_ID { astbuf1 = new AstNode(AST_CELL); @@ -1823,7 +1853,7 @@ simple_behavioral_stmt: // this production creates the obligatory if-else shift/reduce conflict behavioral_stmt: - defattr | assert | wire_decl | param_decl | localparam_decl | + defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | simple_behavioral_stmt ';' | ';' | hierarchical_id attr { diff --git a/tests/svtypes/typedef1.sv b/tests/svtypes/typedef1.sv new file mode 100644 index 000000000..9e5d02364 --- /dev/null +++ b/tests/svtypes/typedef1.sv @@ -0,0 +1,22 @@ +`define STRINGIFY(x) `"x`" +`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) + +module top; + + typedef logic [1:0] uint2_t; + typedef logic signed [3:0] int4_t; + typedef logic signed [7:0] int8_t; + typedef int8_t char_t; + + (* keep *) uint2_t int2 = 2'b10; + (* keep *) int4_t int4 = -1; + (* keep *) int8_t int8 = int4; + (* keep *) char_t ch = int8; + + + always @* assert(int2 == 2'b10); + always @* assert(int4 == 4'b1111); + always @* assert(int8 == 8'b11111111); + always @* assert(ch == 8'b11111111); + +endmodule \ No newline at end of file From c9629516120930aedaf52d72fec5d7fabe51d496 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 21:07:20 +0100 Subject: [PATCH 021/123] sv: Fix typedef parameters Signed-off-by: David Shah --- frontends/ast/simplify.cc | 33 +++++++++++++++++-- frontends/verilog/verilog_parser.y | 21 +++++++++--- tests/svtypes/typedef_param.sv | 22 +++++++++++++ .../{typedef1.sv => typedef_simple.sv} | 3 -- 4 files changed, 70 insertions(+), 9 deletions(-) create mode 100644 tests/svtypes/typedef_param.sv rename tests/svtypes/{typedef1.sv => typedef_simple.sv} (80%) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index b94662bcd..9abd2916d 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -790,8 +790,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(!children[0]->is_custom_type); } - // resolve types of wires and parameters - if (type == AST_WIRE || type == AST_LOCALPARAM || type == AST_PARAMETER) { + // resolve types of wires + if (type == AST_WIRE) { if (is_custom_type) { log_assert(children.size() == 1); log_assert(children[0]->type == AST_WIRETYPE); @@ -820,6 +820,35 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(!is_custom_type); } + // resolve types of parameters + if (type == AST_LOCALPARAM || type == AST_PARAMETER) { + if (is_custom_type) { + log_assert(children.size() == 2); + log_assert(children[1]->type == AST_WIRETYPE); + if (!current_scope.count(children[1]->str)) + log_file_error(filename, linenum, "Unknown identifier `%s' used as type name", children[1]->str.c_str()); + AstNode *resolved_type = current_scope.at(children[1]->str); + if (resolved_type->type != AST_TYPEDEF) + log_file_error(filename, linenum, "`%s' does not name a type", children[1]->str.c_str()); + log_assert(resolved_type->children.size() == 1); + AstNode *templ = resolved_type->children[0]; + delete children[1]; + children.pop_back(); + + is_signed = templ->is_signed; + is_string = templ->is_string; + is_custom_type = templ->is_custom_type; + + range_valid = templ->range_valid; + range_swapped = templ->range_swapped; + range_left = templ->range_left; + range_right = templ->range_right; + for (auto template_child : templ->children) + children.push_back(template_child->clone()); + } + log_assert(!is_custom_type); + } + // resolve constant prefixes if (type == AST_PREFIX) { if (children[0]->type != AST_CONSTANT) { diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index eb091bea6..8cc084fe0 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -327,13 +327,13 @@ single_module_para: astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); append_attr(astbuf1, $1); - } param_signed param_integer param_range single_param_decl | + } int_param_type single_param_decl | attr TOK_LOCALPARAM { if (astbuf1) delete astbuf1; astbuf1 = new AstNode(AST_LOCALPARAM); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); append_attr(astbuf1, $1); - } param_signed param_integer param_range single_param_decl | + } int_param_type single_param_decl | single_param_decl; module_args_opt: @@ -1158,12 +1158,25 @@ param_range: } }; +custom_param_type: + hierarchical_id { + astbuf1->is_custom_type = true; + astbuf1->children.push_back(new AstNode(AST_WIRETYPE)); + astbuf1->children.back()->str = *$1; + }; + +param_type: + param_signed param_integer param_real param_range | custom_param_type; + +int_param_type: + param_signed param_integer param_range | custom_param_type; + param_decl: attr TOK_PARAMETER { astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); append_attr(astbuf1, $1); - } param_signed param_integer param_real param_range param_decl_list ';' { + } param_type param_decl_list ';' { delete astbuf1; }; @@ -1172,7 +1185,7 @@ localparam_decl: astbuf1 = new AstNode(AST_LOCALPARAM); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); append_attr(astbuf1, $1); - } param_signed param_integer param_real param_range param_decl_list ';' { + } param_type param_decl_list ';' { delete astbuf1; }; diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv new file mode 100644 index 000000000..13a522f19 --- /dev/null +++ b/tests/svtypes/typedef_param.sv @@ -0,0 +1,22 @@ +`define STRINGIFY(x) `"x`" +`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) + +module top; + + typedef logic [1:0] uint2_t; + typedef logic signed [3:0] int4_t; + typedef logic signed [7:0] int8_t; + typedef int8_t char_t; + + parameter uint2_t int2 = 2'b10; + localparam int4_t int4 = -1; + localparam int8_t int8 = int4; + localparam char_t ch = int8; + + + `STATIC_ASSERT(int2 == 2'b10); + `STATIC_ASSERT(int4 == 4'b1111); + `STATIC_ASSERT(int8 == 8'b11111111); + `STATIC_ASSERT(ch == 8'b11111111); + +endmodule \ No newline at end of file diff --git a/tests/svtypes/typedef1.sv b/tests/svtypes/typedef_simple.sv similarity index 80% rename from tests/svtypes/typedef1.sv rename to tests/svtypes/typedef_simple.sv index 9e5d02364..0cf2c072c 100644 --- a/tests/svtypes/typedef1.sv +++ b/tests/svtypes/typedef_simple.sv @@ -1,6 +1,3 @@ -`define STRINGIFY(x) `"x`" -`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) - module top; typedef logic [1:0] uint2_t; From e70e4afb60a41da6d9f6200b20f36f61c6b993b2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 21:21:21 +0100 Subject: [PATCH 022/123] sv: Fix typedefs in packages Signed-off-by: David Shah --- frontends/ast/simplify.cc | 14 ++++++++++---- tests/svtypes/typedef_package.sv | 11 +++++++++++ 2 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 tests/svtypes/typedef_package.sv diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 9abd2916d..44e32b29c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -796,14 +796,17 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children.size() == 1); log_assert(children[0]->type == AST_WIRETYPE); if (!current_scope.count(children[0]->str)) - log_file_error(filename, linenum, "Unknown identifier `%s' used as type name", children[0]->str.c_str()); + log_file_error(filename, linenum, "Unknown identifier `%s' used as type name\n", children[0]->str.c_str()); AstNode *resolved_type = current_scope.at(children[0]->str); if (resolved_type->type != AST_TYPEDEF) - log_file_error(filename, linenum, "`%s' does not name a type", children[0]->str.c_str()); + log_file_error(filename, linenum, "`%s' does not name a type\n", children[0]->str.c_str()); log_assert(resolved_type->children.size() == 1); AstNode *templ = resolved_type->children[0]; delete_children(); // type reference no longer needed + // Ensure typedef itself is fully simplified + while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + is_reg = templ->is_reg; is_logic = templ->is_logic; is_signed = templ->is_signed; @@ -826,15 +829,18 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children.size() == 2); log_assert(children[1]->type == AST_WIRETYPE); if (!current_scope.count(children[1]->str)) - log_file_error(filename, linenum, "Unknown identifier `%s' used as type name", children[1]->str.c_str()); + log_file_error(filename, linenum, "Unknown identifier `%s' used as type name\n", children[1]->str.c_str()); AstNode *resolved_type = current_scope.at(children[1]->str); if (resolved_type->type != AST_TYPEDEF) - log_file_error(filename, linenum, "`%s' does not name a type", children[1]->str.c_str()); + log_file_error(filename, linenum, "`%s' does not name a type\n", children[1]->str.c_str()); log_assert(resolved_type->children.size() == 1); AstNode *templ = resolved_type->children[0]; delete children[1]; children.pop_back(); + // Ensure typedef itself is fully simplified + while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + is_signed = templ->is_signed; is_string = templ->is_string; is_custom_type = templ->is_custom_type; diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv new file mode 100644 index 000000000..4aa22b6af --- /dev/null +++ b/tests/svtypes/typedef_package.sv @@ -0,0 +1,11 @@ +package pkg; + typedef logic [7:0] uint8_t; +endpackage + +module top; + + (* keep *) pkg::uint8_t a = 8'hAA; + + always @* assert(a == 8'hAA); + +endmodule \ No newline at end of file From 30d23260309ef392a0e69fe5294c38b71ad0692e Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 11:39:15 +0100 Subject: [PATCH 023/123] sv: Add support for memory typedefs Signed-off-by: David Shah --- frontends/ast/simplify.cc | 17 +++++++++++++++-- frontends/verilog/verilog_parser.y | 20 +++++++++++++++++++- tests/svtypes/typedef_memory.sv | 10 ++++++++++ 3 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 tests/svtypes/typedef_memory.sv diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 44e32b29c..a6ac04037 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -785,8 +785,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // resolve typedefs if (type == AST_TYPEDEF) { log_assert(children.size() == 1); - log_assert(children[0]->type == AST_WIRE); - while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + log_assert(children[0]->type == AST_WIRE || children[0]->type == AST_MEMORY); + while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { + did_something = true; + }; log_assert(!children[0]->is_custom_type); } @@ -807,6 +809,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // Ensure typedef itself is fully simplified while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + type = templ->type; is_reg = templ->is_reg; is_logic = templ->is_logic; is_signed = templ->is_signed; @@ -819,6 +822,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_right = templ->range_right; for (auto template_child : templ->children) children.push_back(template_child->clone()); + did_something = true; } log_assert(!is_custom_type); } @@ -841,6 +845,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // Ensure typedef itself is fully simplified while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + if (templ->type == AST_MEMORY) + log_file_error(filename, linenum, "unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str()); is_signed = templ->is_signed; is_string = templ->is_string; is_custom_type = templ->is_custom_type; @@ -851,6 +857,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_right = templ->range_right; for (auto template_child : templ->children) children.push_back(template_child->clone()); + did_something = true; } log_assert(!is_custom_type); } @@ -3074,6 +3081,9 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg uint32_t children_flags = 0; int lhs_children_counter = 0; + if (type == AST_TYPEDEF) + return; // don't touch content of typedefs + if (type == AST_ASSIGN || type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) { // mark all memories that are used in a complex expression on the left side of an assignment @@ -3231,6 +3241,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, if (type == AST_FUNCTION || type == AST_TASK) return false; + if (type == AST_TYPEDEF) + return false; + if (type == AST_MEMINIT && id2ast && mem2reg_set.count(id2ast)) { log_assert(children[0]->type == AST_CONSTANT); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8cc084fe0..ba44d7f3d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1400,7 +1400,7 @@ assign_expr: }; typedef_decl: - TOK_TYPEDEF wire_type range TOK_ID ';' { + TOK_TYPEDEF wire_type range TOK_ID range_or_multirange ';' { astbuf1 = $2; astbuf2 = $3; if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { @@ -1416,6 +1416,24 @@ typedef_decl: frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [:], [+:], or [-:]"); if (astbuf2) astbuf1->children.push_back(astbuf2); + + if ($5 != NULL) { + if (!astbuf2) { + AstNode *rng = new AstNode(AST_RANGE); + rng->children.push_back(AstNode::mkconst_int(0, true)); + rng->children.push_back(AstNode::mkconst_int(0, true)); + astbuf1->children.push_back(rng); + } + astbuf1->type = AST_MEMORY; + auto *rangeNode = $5; + if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) { + // SV array size [n], rewrite as [n-1:0] + rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)); + rangeNode->children.push_back(AstNode::mkconst_int(0, false)); + } + astbuf1->children.push_back(rangeNode); + } + ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1)); ast_stack.back()->children.back()->str = *$4; }; diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv new file mode 100644 index 000000000..c848c3287 --- /dev/null +++ b/tests/svtypes/typedef_memory.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] ram16x4_t[0:15]; + + ram16x4_t mem; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule \ No newline at end of file From af25585170f87506bcc7dbe5afe0fec868290d5b Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 11:46:37 +0100 Subject: [PATCH 024/123] sv: Add support for memories of a typedef Signed-off-by: David Shah --- frontends/ast/simplify.cc | 26 ++++++++++++++++++++------ tests/svtypes/typedef_memory_2.sv | 10 ++++++++++ 2 files changed, 30 insertions(+), 6 deletions(-) create mode 100644 tests/svtypes/typedef_memory_2.sv diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index a6ac04037..aaf1188b4 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -793,9 +793,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } // resolve types of wires - if (type == AST_WIRE) { + if (type == AST_WIRE || type == AST_MEMORY) { if (is_custom_type) { - log_assert(children.size() == 1); + log_assert(children.size() >= 1); log_assert(children[0]->type == AST_WIRETYPE); if (!current_scope.count(children[0]->str)) log_file_error(filename, linenum, "Unknown identifier `%s' used as type name\n", children[0]->str.c_str()); @@ -804,12 +804,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_file_error(filename, linenum, "`%s' does not name a type\n", children[0]->str.c_str()); log_assert(resolved_type->children.size() == 1); AstNode *templ = resolved_type->children[0]; - delete_children(); // type reference no longer needed + // Remove type reference + delete children[0]; + children.erase(children.begin()); // Ensure typedef itself is fully simplified while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; - type = templ->type; + if (type == AST_WIRE) + type = templ->type; is_reg = templ->is_reg; is_logic = templ->is_logic; is_signed = templ->is_signed; @@ -820,8 +823,19 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_swapped = templ->range_swapped; range_left = templ->range_left; range_right = templ->range_right; - for (auto template_child : templ->children) - children.push_back(template_child->clone()); + + // Insert clones children from template at beginning + for (int i = 0; i < GetSize(templ->children); i++) + children.insert(children.begin() + i, templ->children[i]->clone()); + + if (type == AST_MEMORY && GetSize(children) == 1) { + // Single-bit memories must have [0:0] range + AstNode *rng = new AstNode(AST_RANGE); + rng->children.push_back(AstNode::mkconst_int(0, true)); + rng->children.push_back(AstNode::mkconst_int(0, true)); + children.insert(children.begin(), rng); + } + did_something = true; } log_assert(!is_custom_type); diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv new file mode 100644 index 000000000..1e8abb155 --- /dev/null +++ b/tests/svtypes/typedef_memory_2.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] nibble; + + nibble mem[0:15]; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule \ No newline at end of file From 497faf4ec0c078093ecef547965ae9d0fd153edb Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 11:59:33 +0100 Subject: [PATCH 025/123] sv: Add %expect Signed-off-by: David Shah --- frontends/verilog/verilog_parser.y | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index ba44d7f3d..e0a654b76 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -113,6 +113,7 @@ struct specify_rise_fall { %define api.prefix {frontend_verilog_yy} %glr-parser +%expect 22 /* The union is defined in the header, so we need to provide all the * includes it requires From c0bb47beca2fb78670ab14515047a88a677cc608 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 12:11:17 +0100 Subject: [PATCH 026/123] sv: Fix memories of typedefs Signed-off-by: David Shah --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e0a654b76..516fa4138 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1350,7 +1350,7 @@ wire_name: if ($2 != NULL) { if (node->is_input || node->is_output) frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions."); - if (!astbuf2) { + if (!astbuf2 && !node->is_custom_type) { AstNode *rng = new AstNode(AST_RANGE); rng->children.push_back(AstNode::mkconst_int(0, true)); rng->children.push_back(AstNode::mkconst_int(0, true)); From abc155715dbe8db5ee95707f7c243f23954ca139 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 13:00:26 +0100 Subject: [PATCH 027/123] sv: Add test scripts for typedefs Signed-off-by: David Shah --- Makefile | 1 + tests/svtypes/.gitignore | 3 +++ tests/svtypes/run-test.sh | 20 ++++++++++++++++++++ tests/svtypes/typedef_memory.ys | 3 +++ tests/svtypes/typedef_memory_2.ys | 4 ++++ 5 files changed, 31 insertions(+) create mode 100644 tests/svtypes/.gitignore create mode 100755 tests/svtypes/run-test.sh create mode 100644 tests/svtypes/typedef_memory.ys create mode 100644 tests/svtypes/typedef_memory_2.ys diff --git a/Makefile b/Makefile index 2644721be..4dfed54eb 100644 --- a/Makefile +++ b/Makefile @@ -708,6 +708,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/various && bash run-test.sh +cd tests/sat && bash run-test.sh +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT) + +cd tests/svtypes && bash run-test.sh $(SEEDOPT) +cd tests/proc && bash run-test.sh +cd tests/opt && bash run-test.sh +cd tests/aiger && bash run-test.sh $(ABCOPT) diff --git a/tests/svtypes/.gitignore b/tests/svtypes/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/svtypes/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/svtypes/run-test.sh b/tests/svtypes/run-test.sh new file mode 100755 index 000000000..09a30eed1 --- /dev/null +++ b/tests/svtypes/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for x in *.sv; do + if [ ! -f "${x%.sv}.ys" ]; then + echo "all:: check-$x" + echo "check-$x:" + echo " @echo 'Checking $x..'" + echo " @../../yosys -ql ${x%.sv}.log -p \"prep -top top; sat -verify -prove-asserts\" $x" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys new file mode 100644 index 000000000..bc1127dc5 --- /dev/null +++ b/tests/svtypes/typedef_memory.ys @@ -0,0 +1,3 @@ +read -sv typedef_memory.sv +prep -top top +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys new file mode 100644 index 000000000..571e28914 --- /dev/null +++ b/tests/svtypes/typedef_memory_2.ys @@ -0,0 +1,4 @@ +read -sv typedef_memory_2.sv +prep -top top +dump +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file From 1746b6373b55490314bc2e12c6584c4a1cb38a6a Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 13:01:47 +0100 Subject: [PATCH 028/123] Update CHANGELOG and README Signed-off-by: David Shah --- CHANGELOG | 1 + README.md | 2 ++ 2 files changed, 3 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index c1ffaa44a..51d5e1dc9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -50,6 +50,7 @@ Yosys 0.9 .. Yosys 0.9-dev - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) - "synth_ice40 -dsp" to infer DSP blocks - Added latch support to synth_xilinx + - Added support for SystemVerilog typedefs Yosys 0.8 .. Yosys 0.9 ---------------------- diff --git a/README.md b/README.md index fdd4bb410..db7810cb4 100644 --- a/README.md +++ b/README.md @@ -510,6 +510,8 @@ from SystemVerilog: into a design with ``read_verilog``, all its packages are available to SystemVerilog files being read into the same design afterwards. +- typedefs are supported (including inside packages) + - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether ports are inputs or outputs are supported. From 8cc1bee33c04690d729d1a8b8622be05d65f7911 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 16:12:09 +0100 Subject: [PATCH 029/123] sv: Disambiguate interface ports Signed-off-by: David Shah --- frontends/verilog/verilog_parser.y | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 516fa4138..0024d4778 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -113,7 +113,8 @@ struct specify_rise_fall { %define api.prefix {frontend_verilog_yy} %glr-parser -%expect 22 +%expect 21 +%expect-rr 2 /* The union is defined in the header, so we need to provide all the * includes it requires @@ -157,7 +158,7 @@ struct specify_rise_fall { %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY %type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int -%type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list +%type wire_type wire_type_io expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type opt_label opt_sva_label tok_prim_wrapper hierarchical_id %type opt_signed opt_property unique_case_attr %type attr case_attr @@ -395,7 +396,7 @@ module_arg: ast_stack.back()->children.push_back(astbuf2); delete astbuf1; // really only needed if multiple instances of same type. } module_arg_opt_assignment | - attr wire_type range TOK_ID { + attr wire_type_io range TOK_ID { AstNode *node = $2; node->str = *$4; node->port_id = ++port_counter; @@ -479,6 +480,15 @@ wire_type: $$ = astbuf3; }; +wire_type_io: + { + astbuf3 = new AstNode(AST_WIRE); + current_wire_rand = false; + current_wire_const = false; + } io_wire_type_token_list delay { + $$ = astbuf3; + }; + wire_type_token_list: wire_type_token | wire_type_token_list wire_type_token | wire_type_token_io ; @@ -541,6 +551,12 @@ wire_type_token: astbuf3->children.back()->str = *$1; }; +wire_type_token_list_without_io: + wire_type_token | wire_type_token_list wire_type_token; + +io_wire_type_token_list: + wire_type_token_io | wire_type_token_io wire_type_token_list_without_io; + non_opt_range: '[' expr ':' expr ']' { $$ = new AstNode(AST_RANGE); From 5501d9090aaf2d508b2f082f8453effe7fce08df Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 18:40:23 +0100 Subject: [PATCH 030/123] sv: Fix typedefs in blocks Signed-off-by: David Shah --- frontends/ast/simplify.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index aaf1188b4..0ebc183b2 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3002,7 +3002,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma } } - if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0) + if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE) && name_map.count(str) > 0) str = name_map[str]; std::map backup_name_map; @@ -3010,7 +3010,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma for (size_t i = 0; i < children.size(); i++) { AstNode *child = children[i]; if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || - child->type == AST_FUNCTION || child->type == AST_TASK || child->type == AST_CELL) { + child->type == AST_FUNCTION || child->type == AST_TASK || child->type == AST_CELL || child->type == AST_TYPEDEF) { if (backup_name_map.size() == 0) backup_name_map = name_map; std::string new_name = prefix[0] == '\\' ? prefix.substr(1) : prefix; From 9b9d24f15b1b91b64b97e12bd05693f4539762d9 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 18:40:35 +0100 Subject: [PATCH 031/123] sv: Improve tests Signed-off-by: David Shah --- tests/svtypes/typedef_memory.sv | 2 +- tests/svtypes/typedef_memory.ys | 2 +- tests/svtypes/typedef_memory_2.sv | 2 +- tests/svtypes/typedef_memory_2.ys | 2 +- tests/svtypes/typedef_package.sv | 2 +- tests/svtypes/typedef_param.sv | 2 +- tests/svtypes/typedef_scopes.sv | 23 +++++++++++++++++++++++ tests/svtypes/typedef_simple.sv | 2 +- 8 files changed, 30 insertions(+), 7 deletions(-) create mode 100644 tests/svtypes/typedef_scopes.sv diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv index c848c3287..37e63c1d0 100644 --- a/tests/svtypes/typedef_memory.sv +++ b/tests/svtypes/typedef_memory.sv @@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); if (wen) mem[addr] <= wdata; rdata <= mem[addr]; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys index bc1127dc5..d0b8cf5bf 100644 --- a/tests/svtypes/typedef_memory.ys +++ b/tests/svtypes/typedef_memory.ys @@ -1,3 +1,3 @@ read -sv typedef_memory.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv index 1e8abb155..6d65131db 100644 --- a/tests/svtypes/typedef_memory_2.sv +++ b/tests/svtypes/typedef_memory_2.sv @@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); if (wen) mem[addr] <= wdata; rdata <= mem[addr]; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys index 571e28914..0997beeea 100644 --- a/tests/svtypes/typedef_memory_2.ys +++ b/tests/svtypes/typedef_memory_2.ys @@ -1,4 +1,4 @@ read -sv typedef_memory_2.sv prep -top top dump -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv index 4aa22b6af..bee88b7ae 100644 --- a/tests/svtypes/typedef_package.sv +++ b/tests/svtypes/typedef_package.sv @@ -8,4 +8,4 @@ module top; always @* assert(a == 8'hAA); -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv index 13a522f19..d838dd828 100644 --- a/tests/svtypes/typedef_param.sv +++ b/tests/svtypes/typedef_param.sv @@ -19,4 +19,4 @@ module top; `STATIC_ASSERT(int8 == 8'b11111111); `STATIC_ASSERT(ch == 8'b11111111); -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv new file mode 100644 index 000000000..340defbbb --- /dev/null +++ b/tests/svtypes/typedef_scopes.sv @@ -0,0 +1,23 @@ + +typedef logic [3:0] outer_uint4_t; + +module top; + + outer_uint4_t u4_i = 8'hA5; + always @(*) assert(u4_i == 4'h5); + + typedef logic [3:0] inner_type; + inner_type inner_i1 = 8'h5A; + always @(*) assert(inner_i1 == 4'hA); + + if (1) begin: genblock + typedef logic [7:0] inner_type; + inner_type inner_gb_i = 8'hA5; + always @(*) assert(inner_gb_i == 8'hA5); + end + + inner_type inner_i2 = 8'h42; + always @(*) assert(inner_i2 == 4'h2); + + +endmodule diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv index 0cf2c072c..8f89910e5 100644 --- a/tests/svtypes/typedef_simple.sv +++ b/tests/svtypes/typedef_simple.sv @@ -16,4 +16,4 @@ module top; always @* assert(int8 == 8'b11111111); always @* assert(ch == 8'b11111111); -endmodule \ No newline at end of file +endmodule From e46e8753c84ee83f871d5ce116ce4c08dd49a031 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 3 Oct 2019 09:55:43 +0100 Subject: [PATCH 032/123] frontends/ast: code style Signed-off-by: David Shah --- frontends/ast/simplify.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 0ebc183b2..44fd32cdc 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -786,9 +786,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_TYPEDEF) { log_assert(children.size() == 1); log_assert(children[0]->type == AST_WIRE || children[0]->type == AST_MEMORY); - while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { + while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) did_something = true; - }; log_assert(!children[0]->is_custom_type); } From c6d15c9aade55a87595693ecb9170ae8b595e28c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:07:03 -0700 Subject: [PATCH 033/123] Revert "Update doc for equiv_opt" This reverts commit a274b7cc86d4f64541d3d2903b4eeed4616ab1d8. --- passes/equiv/equiv_opt.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index 4ab5b1a3e..9fe3bbd57 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -32,8 +32,7 @@ struct EquivOptPass:public ScriptPass log("\n"); log(" equiv_opt [options] [command]\n"); log("\n"); - log("This command uses temporal induction to check circuit equivalence before and\n"); - log("after an optimization pass.\n"); + log("This command checks circuit equivalence before and after an optimization pass.\n"); log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); @@ -157,7 +156,7 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); - if (!multiclock || help_mode) + else run("async2sync", "(only without -multiclock)"); run("equiv_make gold gate equiv"); if (help_mode) From 8765ec3c27f38e6fb57d057be9605788e144388b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:07:15 -0700 Subject: [PATCH 034/123] Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys" This reverts commit a39505e329cc05dbd4ad624a1cf0f6caf664fd9a. --- passes/equiv/equiv_opt.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index 9fe3bbd57..d4c7f7953 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -156,8 +156,6 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); - else - run("async2sync", "(only without -multiclock)"); run("equiv_make gold gate equiv"); if (help_mode) run("equiv_induct [-undef] equiv"); From 5d680590d6bccd929ed3909248dbb73fb3876e65 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:30:33 -0700 Subject: [PATCH 035/123] Use equiv_opt -async2sync for xilinx --- tests/xilinx/latches.ys | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index ac1102896..bd1dffd21 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -2,9 +2,7 @@ read_verilog latches.v proc flatten -equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -async2sync -equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load preopt synth_xilinx From 7a6dec1cef9c6a44dafe83d884abaf06dc77ab07 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:30:51 -0700 Subject: [PATCH 036/123] Add new -async2sync option --- passes/equiv/equiv_opt.cc | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index d4c7f7953..d13e46ce4 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -58,7 +58,7 @@ struct EquivOptPass:public ScriptPass } std::string command, techmap_opts; - bool assert, undef, multiclock; + bool assert, undef, multiclock, async2sync; void clear_flags() YS_OVERRIDE { @@ -67,6 +67,7 @@ struct EquivOptPass:public ScriptPass assert = false; undef = false; multiclock = false; + async2sync = false; } void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE @@ -100,6 +101,10 @@ struct EquivOptPass:public ScriptPass multiclock = true; continue; } + if (args[argidx] == "-async2sync") { + async2sync = true; + continue; + } break; } @@ -119,6 +124,9 @@ struct EquivOptPass:public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (async2sync && multiclock) + log_cmd_error("The '-async2sync' and '-multiclock' options are mutually exclusive!\n"); + log_header(design, "Executing EQUIV_OPT pass.\n"); log_push(); @@ -156,6 +164,8 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); + if (async2sync || help_mode) + run("async2sync", "(only with -async2sync)"); run("equiv_make gold gate equiv"); if (help_mode) run("equiv_induct [-undef] equiv"); From bd5889640bbcbb11c80360893fcf17d9399cef8a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:45:53 -0700 Subject: [PATCH 037/123] Disable equiv check for ice40 latches --- tests/ice40/latches.ys | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index f3562559e..708734e44 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,14 +1,11 @@ read_verilog latches.v -design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +# Can't run any sort of equivalence check because latches are blown to LUTs +#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load read +#design -load preopt synth_ice40 cd top select -assert-count 4 t:SB_LUT4 From a9efd2e81cd502665ee034f64c85b11e34dfd9bb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:51:53 -0700 Subject: [PATCH 038/123] Restore part of doc --- passes/equiv/equiv_opt.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index d13e46ce4..ec1200488 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -32,7 +32,8 @@ struct EquivOptPass:public ScriptPass log("\n"); log(" equiv_opt [options] [command]\n"); log("\n"); - log("This command checks circuit equivalence before and after an optimization pass.\n"); + log("This command uses temporal induction to check circuit equivalence before and\n"); + log("after an optimization pass.\n"); log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); From 045f34403889b69f3ac3ac08d96e5cf1fae787d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 11:11:50 -0700 Subject: [PATCH 039/123] Use `sat -tempinduct` and comments for why equiv_opt not sufficient --- tests/various/peepopt.ys | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 4b130578b..ee5ad8a1a 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -188,6 +188,13 @@ endmodule EOT proc +# NB: equiv_opt uses equiv_induct which covers +# only the induction half of temporal induction +# --- missing the base-case half +# This makes it akin to `sat -tempinduct-inductonly` +# instead of `sat -tempinduct-baseonly` or +# `sat -tempinduct` which is necessary for this +# testcase #equiv_opt -assert peepopt design -save gold @@ -197,7 +204,7 @@ design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -seq 1 -verify -prove-asserts -show-ports miter +sat -tempinduct -verify -prove-asserts -show-ports miter design -load gate select -assert-count 1 t:$dff r:WIDTH=4 %i From d19f765a581ac465a7f7cea22f1d96c9da9cbe01 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:41:53 +0200 Subject: [PATCH 040/123] Removed alu and div_mod tests as agreed --- tests/ecp5/alu.v | 19 ------------------- tests/ecp5/alu.ys | 13 ------------- tests/ecp5/div_mod.v | 13 ------------- tests/ecp5/div_mod.ys | 12 ------------ 4 files changed, 57 deletions(-) delete mode 100644 tests/ecp5/alu.v delete mode 100644 tests/ecp5/alu.ys delete mode 100644 tests/ecp5/div_mod.v delete mode 100644 tests/ecp5/div_mod.ys diff --git a/tests/ecp5/alu.v b/tests/ecp5/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/ecp5/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys deleted file mode 100644 index c2950b164..000000000 --- a/tests/ecp5/alu.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 32 t:CCU2C -select -assert-count 242 t:L6MUX21 -select -assert-count 1127 t:LUT4 -select -assert-count 417 t:PFUMX -select -assert-count 32 t:TRELLIS_FF -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ecp5/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys deleted file mode 100644 index 9efb00701..000000000 --- a/tests/ecp5/div_mod.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 28 t:CCU2C -select -assert-count 26 t:L6MUX21 -select -assert-count 138 t:LUT4 -select -assert-count 60 t:PFUMX -select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D From 9e8175fc759478a7a496ac0d492cb4b6d0f13799 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:42:29 +0200 Subject: [PATCH 041/123] Check flops one by one --- tests/ecp5/adffs.v | 40 ---------------------------------------- tests/ecp5/adffs.ys | 41 ++++++++++++++++++++++++++++++++++++----- tests/ecp5/dffs.v | 22 ---------------------- tests/ecp5/dffs.ys | 18 ++++++++++++++---- 4 files changed, 50 insertions(+), 71 deletions(-) diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v index 05e68caf7..223b52d21 100644 --- a/tests/ecp5/adffs.v +++ b/tests/ecp5/adffs.v @@ -45,43 +45,3 @@ module ndffnr else q <= d; endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index fc1363a32..658f302d0 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,9 +1,40 @@ read_verilog adffs.v +design -save read + proc -flatten -equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +hierarchy -top adff +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 4 t:TRELLIS_FF -select -assert-count 3 t:LUT4 +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +proc +hierarchy -top adffn +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top dffs +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top ndffnr +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v index d97840c43..3418787c9 100644 --- a/tests/ecp5/dffs.v +++ b/tests/ecp5/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 5510bb440..93b8595ad 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,9 +1,19 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 2 t:TRELLIS_FF +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D \ No newline at end of file From abb5a3a44df18a6ca18b6998f4c35aafc4284df8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:44:10 +0200 Subject: [PATCH 042/123] Check for MULT18X18D, since that is working now --- tests/ecp5/macc.ys | 12 +++++------- tests/ecp5/mul.ys | 13 ++++++------- 2 files changed, 11 insertions(+), 14 deletions(-) diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index bc6340509..f60281a54 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,15 +1,13 @@ read_verilog macc.v proc hierarchy -top top -#Failed because of 14 unproven cells. -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -#equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +# Blocked by issue #1358 (Missing ECP5 simulation models) +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18D select -assert-count 4 t:CCU2C -select -assert-count 6 t:L6MUX21 -select -assert-count 49 t:LUT4 -select -assert-count 19 t:PFUMX select -assert-count 7 t:TRELLIS_FF -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D +select -assert-none t:CCU2C t:MULT18X18D t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys index 0e8d6908f..132340664 100644 --- a/tests/ecp5/mul.ys +++ b/tests/ecp5/mul.ys @@ -1,11 +1,10 @@ read_verilog mul.v hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +# Blocked by issue #1358 (Missing ECP5 simulation models) +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:CCU2C -select -assert-count 46 t:L6MUX21 -select -assert-count 169 t:LUT4 -select -assert-count 72 t:PFUMX - -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D +select -assert-count 1 t:MULT18X18D +select -assert-none t:MULT18X18D %% t:* %D From d6ef9b1a6b47e740dba948e5f2fcf456d7ee79cf Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:45:58 +0200 Subject: [PATCH 043/123] Cleaned verilog code from not used defines --- tests/ecp5/shifter.v | 6 ------ 1 file changed, 6 deletions(-) diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v index c55632552..04ae49d83 100644 --- a/tests/ecp5/shifter.v +++ b/tests/ecp5/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule From 3c40c810307c2bed62527f4f067790edc4ac8823 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:52:54 +0200 Subject: [PATCH 044/123] Test muxes synth one by one --- tests/ecp5/mux.v | 34 ---------------------------------- tests/ecp5/mux.ys | 45 ++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 40 insertions(+), 39 deletions(-) diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v index 0814b733e..782424a9b 100644 --- a/tests/ecp5/mux.v +++ b/tests/ecp5/mux.v @@ -64,37 +64,3 @@ assign Y = D[S]; endmodule - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys index 7d40c9cf1..eada276ba 100644 --- a/tests/ecp5/mux.ys +++ b/tests/ecp5/mux.ys @@ -1,11 +1,46 @@ read_verilog mux.v +design -save read + proc -flatten +hierarchy -top mux2 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 32 t:LUT4 -select -assert-count 8 t:L6MUX21 -select -assert-count 14 t:PFUMX +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top mux4 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:L6MUX21 +select -assert-count 4 t:LUT4 +select -assert-count 2 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:L6MUX21 +select -assert-count 7 t:LUT4 +select -assert-count 2 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D + +design -load read +proc +hierarchy -top mux16 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 8 t:L6MUX21 +select -assert-count 26 t:LUT4 +select -assert-count 12 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D From 3358b2f18597c59ee3cac5f123f954ca79e0baad Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:53:54 +0200 Subject: [PATCH 045/123] Removed top module where not needed --- tests/ecp5/fsm.v | 18 ------------------ tests/ecp5/fsm.ys | 4 ++-- tests/ecp5/tribuf.v | 15 --------------- tests/ecp5/tribuf.ys | 4 ++-- 4 files changed, 4 insertions(+), 37 deletions(-) diff --git a/tests/ecp5/fsm.v b/tests/ecp5/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/ecp5/fsm.v +++ b/tests/ecp5/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 6368edc57..ded91e5f7 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -1,10 +1,10 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 select -assert-count 13 t:LUT4 select -assert-count 5 t:PFUMX diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v index 870a02584..90dd314e4 100644 --- a/tests/ecp5/tribuf.v +++ b/tests/ecp5/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); assign o = en ? i : 1'bz; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys index f454a0c02..a6e9c9598 100644 --- a/tests/ecp5/tribuf.ys +++ b/tests/ecp5/tribuf.ys @@ -1,9 +1,9 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D From 7785f23719cdbcae6816415cf2dc124aba312c66 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:31:51 +0200 Subject: [PATCH 046/123] Check latches type one by one --- tests/ecp5/latches.v | 34 ---------------------------------- tests/ecp5/latches.ys | 31 +++++++++++++++++++++++++------ 2 files changed, 25 insertions(+), 40 deletions(-) diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/ecp5/latches.v +++ b/tests/ecp5/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index b9d8faf87..f32998232 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -1,16 +1,35 @@ + read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 + +select -assert-none t:LUT4 %% t:* %D + design -load read +proc +hierarchy -top latchn +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -cd top -select -assert-count 4 t:LUT4 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 + +select -assert-none t:LUT4 %% t:* %D + + +design -load read +proc +hierarchy -top latchsr +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ecp5 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:LUT4 select -assert-count 1 t:PFUMX + select -assert-none t:LUT4 t:PFUMX %% t:* %D From 1435b9bf97bc5c4e625bd3ef5db19065a0af2632 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:55:13 +0200 Subject: [PATCH 047/123] remove alu test --- tests/anlogic/alu.v | 19 ------------------- tests/anlogic/alu.ys | 17 ----------------- 2 files changed, 36 deletions(-) delete mode 100644 tests/anlogic/alu.v delete mode 100644 tests/anlogic/alu.ys diff --git a/tests/anlogic/alu.v b/tests/anlogic/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/anlogic/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/anlogic/alu.ys b/tests/anlogic/alu.ys deleted file mode 100644 index 532ce82d5..000000000 --- a/tests/anlogic/alu.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 66 t:AL_MAP_ADDER -select -assert-count 32 t:AL_MAP_LUT1 -select -assert-count 23 t:AL_MAP_LUT2 -select -assert-count 61 t:AL_MAP_LUT3 -select -assert-count 209 t:AL_MAP_LUT4 -select -assert-count 100 t:AL_MAP_LUT5 -select -assert-count 79 t:AL_MAP_LUT6 -select -assert-count 32 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D From 3d3479b0af0d2d59708a0828cfa785257c52d6fd Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:57:47 +0200 Subject: [PATCH 048/123] Cleanup top modules and not used defines --- tests/anlogic/fsm.v | 18 ------------------ tests/anlogic/fsm.ys | 6 +++--- tests/anlogic/shifter.v | 6 ------ tests/anlogic/tribuf.v | 15 --------------- tests/anlogic/tribuf.ys | 4 ++-- 5 files changed, 5 insertions(+), 44 deletions(-) diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/anlogic/fsm.v +++ b/tests/anlogic/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys index 6eb7b9a71..76a5d3e43 100644 --- a/tests/anlogic/fsm.ys +++ b/tests/anlogic/fsm.ys @@ -1,12 +1,12 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc -flatten +#flatten #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v index c55632552..04ae49d83 100644 --- a/tests/anlogic/shifter.v +++ b/tests/anlogic/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v index 870a02584..90dd314e4 100644 --- a/tests/anlogic/tribuf.v +++ b/tests/anlogic/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); assign o = en ? i : 1'bz; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys index 663e93fb2..0eb1338ac 100644 --- a/tests/anlogic/tribuf.ys +++ b/tests/anlogic/tribuf.ys @@ -1,9 +1,9 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc flatten equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D From 91ad3ab717159da311b72531f4b9c77a7522702a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:00:49 +0200 Subject: [PATCH 049/123] check ff's separately --- tests/anlogic/dffs.v | 22 ---------------------- tests/anlogic/dffs.ys | 18 ++++++++++++++---- 2 files changed, 14 insertions(+), 26 deletions(-) diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v index d97840c43..3418787c9 100644 --- a/tests/anlogic/dffs.v +++ b/tests/anlogic/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys index a15c6f24e..38dffa326 100644 --- a/tests/anlogic/dffs.ys +++ b/tests/anlogic/dffs.ys @@ -1,10 +1,20 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 2 t:AL_MAP_SEQ +select -assert-count 1 t:AL_MAP_SEQ select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D From 3238ee7d354aed51eb61ce5a8c2799f56f2cb4b2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:04:18 +0200 Subject: [PATCH 050/123] check muxes per type --- tests/anlogic/mux.v | 35 ----------------------------------- tests/anlogic/mux.ys | 44 +++++++++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 42 deletions(-) diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v index 0814b733e..27bc0bf0b 100644 --- a/tests/anlogic/mux.v +++ b/tests/anlogic/mux.v @@ -63,38 +63,3 @@ module mux16 (D, S, Y); assign Y = D[S]; endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys index 84a8bcccf..354fc836c 100644 --- a/tests/anlogic/mux.ys +++ b/tests/anlogic/mux.ys @@ -1,12 +1,42 @@ read_verilog mux.v +design -save read + proc -flatten +hierarchy -top mux2 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 4 t:AL_MAP_LUT4 -select -assert-count 4 t:AL_MAP_LUT5 -select -assert-count 1 t:AL_MAP_LUT6 -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D +select -assert-none t:AL_MAP_LUT3 %% t:* %D + +design -load read +proc +hierarchy -top mux4 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT6 %% t:* %D + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 3 t:AL_MAP_LUT4 +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D + +design -load read +proc +hierarchy -top mux16 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT6 %% t:* %D From a5844e3ceb76152d1e87ad8fdf1c71553238ef64 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:08:42 +0200 Subject: [PATCH 051/123] split latches into separate checks --- tests/anlogic/latches.v | 34 ---------------------------------- tests/anlogic/latches.ys | 31 ++++++++++++++++++++++++------- 2 files changed, 24 insertions(+), 41 deletions(-) diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/anlogic/latches.v +++ b/tests/anlogic/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys index b5e52cf16..ae9e15ff8 100644 --- a/tests/anlogic/latches.ys +++ b/tests/anlogic/latches.ys @@ -2,15 +2,32 @@ read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp +# Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + design -load read +proc +hierarchy -top latchn +# Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic -cd top -select -assert-count 2 t:AL_MAP_LUT3 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + + +design -load read +proc +hierarchy -top latchsr +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT5 -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D + +select -assert-none t:AL_MAP_LUT5 %% t:* %D From 03a3deec43ef4e92b251ea4bceaadc77c8044df0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:09:59 +0200 Subject: [PATCH 052/123] Cleanup and formating --- tests/anlogic/add_sub.ys | 2 +- tests/anlogic/counter.ys | 2 +- tests/anlogic/fsm.ys | 1 + tests/anlogic/shifter.ys | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys index 55c090506..994cd0d03 100644 --- a/tests/anlogic/add_sub.ys +++ b/tests/anlogic/add_sub.ys @@ -5,5 +5,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 10 t:AL_MAP_ADDER select -assert-count 4 t:AL_MAP_LUT1 -select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys index 5210221e3..036fdba46 100644 --- a/tests/anlogic/counter.ys +++ b/tests/anlogic/counter.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module select -assert-count 9 t:AL_MAP_ADDER select -assert-count 8 t:AL_MAP_SEQ -select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D +select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys index 76a5d3e43..452ef9251 100644 --- a/tests/anlogic/fsm.ys +++ b/tests/anlogic/fsm.ys @@ -11,4 +11,5 @@ select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 select -assert-count 6 t:AL_MAP_SEQ + select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys index edd89b344..5eaed30a3 100644 --- a/tests/anlogic/shifter.ys +++ b/tests/anlogic/shifter.ys @@ -6,4 +6,5 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 8 t:AL_MAP_SEQ + select -assert-none t:AL_MAP_SEQ %% t:* %D From c0b14cfea7c5650ddbc28d69de4749f845954dc7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 16:29:46 +0200 Subject: [PATCH 053/123] Fixes for MSVC build --- frontends/rpc/rpc_frontend.cc | 8 ++++++-- passes/pmgen/xilinx_dsp.cc | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 83e1353b0..add17c243 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -28,14 +28,13 @@ #include #include #include +extern char **environ; #endif #include "libs/json11/json11.hpp" #include "libs/sha1/sha1.h" #include "kernel/yosys.h" -extern char **environ; - YOSYS_NAMESPACE_BEGIN #if defined(_WIN32) @@ -238,6 +237,11 @@ struct RpcModule : RTLIL::Module { #if defined(_WIN32) +#if defined(_MSC_VER) +#include +typedef SSIZE_T ssize_t; +#endif + struct HandleRpcServer : RpcServer { HANDLE hsend, hrecv; diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 11c7e5ea8..3ff921957 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -20,6 +20,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN From 84f978bdc20494167a6a2c5f654b96c4f565a5e0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 10:17:46 -0700 Subject: [PATCH 054/123] Add -async2sync to help text as per @daveshah1 --- passes/equiv/equiv_opt.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index ec1200488..c7e6d71a6 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -50,6 +50,9 @@ struct EquivOptPass:public ScriptPass log(" -multiclock\n"); log(" run clk2fflogic before equivalence checking.\n"); log("\n"); + log(" -async2sync\n"); + log(" run async2sync before equivalence checking.\n"); + log("\n"); log(" -undef\n"); log(" enable modelling of undef states during equiv_induct.\n"); log("\n"); @@ -166,7 +169,7 @@ struct EquivOptPass:public ScriptPass if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); if (async2sync || help_mode) - run("async2sync", "(only with -async2sync)"); + run("async2sync", " (only with -async2sync)"); run("equiv_make gold gate equiv"); if (help_mode) run("equiv_induct [-undef] equiv"); From c0f54d3fd5e2492afbe1717a67ea78f3be7f6b39 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 10:34:16 -0700 Subject: [PATCH 055/123] Ohmilord this wasn't added all this time!?! --- techlibs/ice40/abc_model.v | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 techlibs/ice40/abc_model.v diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc_model.v new file mode 100644 index 000000000..89961b51d --- /dev/null +++ b/techlibs/ice40/abc_model.v @@ -0,0 +1,29 @@ +(* abc9_box_id = 1, lib_whitebox *) +module \$__ICE40_CARRY_WRAPPER ( + (* abc_carry *) + output CO, + output O, + input A, B, + (* abc_carry *) + input CI, + input I0, I3 +); + parameter LUT = 0; + SB_CARRY carry ( + .I0(A), + .I1(B), + .CI(CI), + .CO(CO) + ); + SB_LUT4 #( + .LUT_INIT(LUT) + ) adder ( + .I0(I0), + .I1(A), + .I2(B), + .I3(I3), + .O(O) + ); +endmodule + + From 4e11782cde412ce80ee8125dd9d55fe21945737f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 10:36:02 -0700 Subject: [PATCH 056/123] Oops --- techlibs/ice40/abc_model.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc_model.v index 89961b51d..8e1827043 100644 --- a/techlibs/ice40/abc_model.v +++ b/techlibs/ice40/abc_model.v @@ -1,4 +1,4 @@ -(* abc9_box_id = 1, lib_whitebox *) +(* abc_box_id = 1, lib_whitebox *) module \$__ICE40_CARRY_WRAPPER ( (* abc_carry *) output CO, From 9fef1df3c1431cff2e097a10a502f77f04986a60 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 10:48:44 -0700 Subject: [PATCH 057/123] Panic over. Model was elsewhere. Re-arrange for consistency --- techlibs/ecp5/synth_ecp5.cc | 1 + techlibs/ice40/Makefile.inc | 1 + techlibs/ice40/abc_model.v | 2 -- techlibs/ice40/cells_sim.v | 28 ---------------------------- techlibs/ice40/synth_ice40.cc | 3 ++- 5 files changed, 4 insertions(+), 31 deletions(-) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 1f5b1cb6b..67d2f483c 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -311,6 +311,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { + run("read_verilog -icells -lib +/ecp5/abc_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200"); else diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index 92a9956ea..0fbca9034 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -28,6 +28,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_model.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box)) diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc_model.v index 8e1827043..fe31b8811 100644 --- a/techlibs/ice40/abc_model.v +++ b/techlibs/ice40/abc_model.v @@ -25,5 +25,3 @@ module \$__ICE40_CARRY_WRAPPER ( .O(O) ); endmodule - - diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 8e5e0358e..16a893226 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -145,34 +145,6 @@ module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -(* abc_box_id = 1, lib_whitebox *) -module \$__ICE40_CARRY_WRAPPER ( - (* abc_carry *) - output CO, - output O, - input A, B, - (* abc_carry *) - input CI, - input I0, I3 -); - parameter LUT = 0; - SB_CARRY carry ( - .I0(A), - .I1(B), - .CI(CI), - .CO(CO) - ); - SB_LUT4 #( - .LUT_INIT(LUT) - ) adder ( - .I0(I0), - .I1(A), - .I2(B), - .I3(I3), - .O(O) - ); -endmodule - // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 841f10244..2e4684c19 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass define = "-D ICE40_U"; else define = "-D ICE40_HX"; - run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v"); + run("read_verilog " + define + " -lib +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); run("proc"); } @@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { + run("read_verilog -icells -lib +/ice40/abc_model.v"); int wire_delay; if (device_opt == "lp") wire_delay = 400; From aae2b9fd9c8dc915fadacc24962436dd7aedff36 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 11:04:10 -0700 Subject: [PATCH 058/123] Rename abc_* names/attributes to more precisely be abc9_* --- backends/aiger/xaiger.cc | 18 +- frontends/aiger/aigerparse.cc | 8 +- passes/techmap/abc9.cc | 130 +++++++-------- techlibs/ecp5/Makefile.inc | 12 +- techlibs/ecp5/{abc_5g.box => abc9_5g.box} | 2 +- techlibs/ecp5/{abc_5g.lut => abc9_5g.lut} | 0 .../{abc_5g_nowide.lut => abc9_5g_nowide.lut} | 0 techlibs/ecp5/{abc_map.v => abc9_map.v} | 2 +- techlibs/ecp5/abc9_model.v | 5 + techlibs/ecp5/{abc_unmap.v => abc9_unmap.v} | 2 +- techlibs/ecp5/abc_model.v | 5 - techlibs/ecp5/cells_sim.v | 12 +- techlibs/ecp5/synth_ecp5.cc | 10 +- techlibs/ice40/Makefile.inc | 14 +- techlibs/ice40/{abc_hx.box => abc9_hx.box} | 0 techlibs/ice40/{abc_hx.lut => abc9_hx.lut} | 0 techlibs/ice40/{abc_lp.box => abc9_lp.box} | 0 techlibs/ice40/{abc_lp.lut => abc9_lp.lut} | 0 techlibs/ice40/{abc_model.v => abc9_model.v} | 6 +- techlibs/ice40/{abc_u.box => abc9_u.box} | 0 techlibs/ice40/{abc_u.lut => abc9_u.lut} | 0 techlibs/ice40/cells_sim.v | 157 +++++++++--------- techlibs/ice40/synth_ice40.cc | 4 +- techlibs/xilinx/Makefile.inc | 12 +- techlibs/xilinx/{abc_map.v => abc9_map.v} | 66 ++++---- techlibs/xilinx/{abc_model.v => abc9_model.v} | 40 ++--- techlibs/xilinx/{abc_unmap.v => abc9_unmap.v} | 14 +- techlibs/xilinx/{abc_xc7.box => abc9_xc7.box} | 24 +-- techlibs/xilinx/{abc_xc7.lut => abc9_xc7.lut} | 0 ...abc_xc7_nowide.lut => abc9_xc7_nowide.lut} | 0 techlibs/xilinx/cells_sim.v | 38 ++--- techlibs/xilinx/synth_xilinx.cc | 13 +- techlibs/xilinx/xc6s_brams_bb.v | 8 + techlibs/xilinx/xc7_brams_bb.v | 16 +- 34 files changed, 313 insertions(+), 305 deletions(-) rename techlibs/ecp5/{abc_5g.box => abc9_5g.box} (96%) rename techlibs/ecp5/{abc_5g.lut => abc9_5g.lut} (100%) rename techlibs/ecp5/{abc_5g_nowide.lut => abc9_5g_nowide.lut} (100%) rename techlibs/ecp5/{abc_map.v => abc9_map.v} (89%) create mode 100644 techlibs/ecp5/abc9_model.v rename techlibs/ecp5/{abc_unmap.v => abc9_unmap.v} (52%) delete mode 100644 techlibs/ecp5/abc_model.v rename techlibs/ice40/{abc_hx.box => abc9_hx.box} (100%) rename techlibs/ice40/{abc_hx.lut => abc9_hx.lut} (100%) rename techlibs/ice40/{abc_lp.box => abc9_lp.box} (100%) rename techlibs/ice40/{abc_lp.lut => abc9_lp.lut} (100%) rename techlibs/ice40/{abc_model.v => abc9_model.v} (79%) rename techlibs/ice40/{abc_u.box => abc9_u.box} (100%) rename techlibs/ice40/{abc_u.lut => abc9_u.lut} (100%) rename techlibs/xilinx/{abc_map.v => abc9_map.v} (88%) rename techlibs/xilinx/{abc_model.v => abc9_model.v} (83%) rename techlibs/xilinx/{abc_unmap.v => abc9_unmap.v} (92%) rename techlibs/xilinx/{abc_xc7.box => abc9_xc7.box} (99%) rename techlibs/xilinx/{abc_xc7.lut => abc9_xc7.lut} (100%) rename techlibs/xilinx/{abc_xc7_nowide.lut => abc9_xc7_nowide.lut} (100%) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 4018cc9de..46890b071 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -203,7 +203,7 @@ struct XAigerWriter // box ordering, but not individual AIG cells dict> bit_drivers, bit_users; TopoSort toposort; - bool abc_box_seen = false; + bool abc9_box_seen = false; for (auto cell : module->selected_cells()) { if (cell->type == "$_NOT_") @@ -242,8 +242,8 @@ struct XAigerWriter log_assert(!holes_mode); RTLIL::Module* inst_module = module->design->module(cell->type); - if (inst_module && inst_module->attributes.count("\\abc_box_id")) { - abc_box_seen = true; + if (inst_module && inst_module->attributes.count("\\abc9_box_id")) { + abc9_box_seen = true; if (!holes_mode) { toposort.node(cell->name); @@ -291,10 +291,10 @@ struct XAigerWriter if (is_output) { int arrival = 0; if (port_wire) { - auto it = port_wire->attributes.find("\\abc_arrival"); + auto it = port_wire->attributes.find("\\abc9_arrival"); if (it != port_wire->attributes.end()) { if (it->second.flags != 0) - log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type)); + log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type)); arrival = it->second.as_int(); } } @@ -318,7 +318,7 @@ struct XAigerWriter //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); } - if (abc_box_seen) { + if (abc9_box_seen) { for (auto &it : bit_users) if (bit_drivers.count(it.first)) for (auto driver_cell : bit_drivers.at(it.first)) @@ -347,7 +347,7 @@ struct XAigerWriter log_assert(cell); RTLIL::Module* box_module = module->design->module(cell->type); - if (!box_module || !box_module->attributes.count("\\abc_box_id")) + if (!box_module || !box_module->attributes.count("\\abc9_box_id")) continue; bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); @@ -398,7 +398,7 @@ struct XAigerWriter else { Wire *wire = module->addWire(NEW_ID, GetSize(w)); if (blackbox) - wire->set_bool_attribute(ID(abc_padding)); + wire->set_bool_attribute(ID(abc9_padding)); rhs = wire; cell->setPort(port_name, rhs); } @@ -666,7 +666,7 @@ struct XAigerWriter write_h_buffer(box_inputs); write_h_buffer(box_outputs); - write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int()); + write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int()); write_h_buffer(box_count++); } diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 5a1da4db1..cf060193d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -740,22 +740,22 @@ void AigerReader::post_process() log_assert(box_module); if (seen_boxes.insert(cell->type).second) { - auto it = box_module->attributes.find("\\abc_carry"); + auto it = box_module->attributes.find("\\abc9_carry"); if (it != box_module->attributes.end()) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; auto carry_in_out = it->second.decode_string(); auto pos = carry_in_out.find(','); if (pos == std::string::npos) - log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type)); + log_error("'abc9_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type)); auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos)); carry_in = box_module->wire(carry_in_name); if (!carry_in || !carry_in->port_input) - log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str()); + log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str()); auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1)); carry_out = box_module->wire(carry_out_name); if (!carry_out || !carry_out->port_output) - log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str()); + log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str()); auto &ports = box_module->ports; for (auto jt = ports.begin(); jt != ports.end(); ) { diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 09d6e9670..1ebdaa29e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -71,21 +71,21 @@ RTLIL::Module *module; bool clk_polarity, en_polarity; RTLIL::SigSpec clk_sig, en_sig; -inline std::string remap_name(RTLIL::IdString abc_name) +inline std::string remap_name(RTLIL::IdString abc9_name) { - return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1); + return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1); } void handle_loops(RTLIL::Design *design) { - Pass::call(design, "scc -set_attr abc_scc_id {}"); + Pass::call(design, "scc -set_attr abc9_scc_id {}"); // For every unique SCC found, (arbitrarily) find the first // cell in the component, and select (and mark) all its output // wires pool ids_seen; for (auto cell : module->cells()) { - auto it = cell->attributes.find(ID(abc_scc_id)); + auto it = cell->attributes.find(ID(abc9_scc_id)); if (it != cell->attributes.end()) { auto r = ids_seen.insert(it->second); if (r.second) { @@ -105,7 +105,7 @@ void handle_loops(RTLIL::Design *design) log_assert(w->port_input); log_assert(b.offset < GetSize(w)); } - w->set_bool_attribute(ID(abc_scc_break)); + w->set_bool_attribute(ID(abc9_scc_break)); module->swap_names(b.wire, w); c.second = RTLIL::SigBit(w, b.offset); } @@ -118,7 +118,7 @@ void handle_loops(RTLIL::Design *design) module->fixup_ports(); } -std::string add_echos_to_abc_cmd(std::string str) +std::string add_echos_to_abc9_cmd(std::string str) { std::string new_str, token; for (size_t i = 0; i < str.size(); i++) { @@ -140,7 +140,7 @@ std::string add_echos_to_abc_cmd(std::string str) return new_str; } -std::string fold_abc_cmd(std::string str) +std::string fold_abc9_cmd(std::string str) { std::string token, new_str = " "; int char_counter = 10; @@ -184,7 +184,7 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho return text; } -struct abc_output_filter +struct abc9_output_filter { bool got_cr; int escape_seq_state; @@ -192,7 +192,7 @@ struct abc_output_filter std::string tempdir_name; bool show_tempdir; - abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir) + abc9_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir) { got_cr = false; escape_seq_state = 0; @@ -293,68 +293,68 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n", module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); - std::string abc_script; + std::string abc9_script; if (!lut_costs.empty()) { - abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); + abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); if (!box_file.empty()) - abc_script += stringf("read_box -v %s; ", box_file.c_str()); + abc9_script += stringf("read_box -v %s; ", box_file.c_str()); } else if (!lut_file.empty()) { - abc_script += stringf("read_lut %s; ", lut_file.c_str()); + abc9_script += stringf("read_lut %s; ", lut_file.c_str()); if (!box_file.empty()) - abc_script += stringf("read_box -v %s; ", box_file.c_str()); + abc9_script += stringf("read_box -v %s; ", box_file.c_str()); } else log_abort(); - abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str()); + abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str()); if (!script_file.empty()) { if (script_file[0] == '+') { for (size_t i = 1; i < script_file.size(); i++) if (script_file[i] == '\'') - abc_script += "'\\''"; + abc9_script += "'\\''"; else if (script_file[i] == ',') - abc_script += " "; + abc9_script += " "; else - abc_script += script_file[i]; + abc9_script += script_file[i]; } else - abc_script += stringf("source %s", script_file.c_str()); + abc9_script += stringf("source %s", script_file.c_str()); } else if (!lut_costs.empty() || !lut_file.empty()) { //bool all_luts_cost_same = true; //for (int this_cost : lut_costs) // if (this_cost != lut_costs.front()) // all_luts_cost_same = false; - abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT; + abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT; //if (all_luts_cost_same && !fast_mode) - // abc_script += "; lutpack {S}"; + // abc9_script += "; lutpack {S}"; } else log_abort(); //if (script_file.empty() && !delay_target.empty()) - // for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1)) - // abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8); + // for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1)) + // abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8); - for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos)) - abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3); + for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos)) + abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3); - //for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) - // abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3); + //for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos)) + // abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3); - for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos)) - abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3); + for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos)) + abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3); - abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str()); - abc_script = add_echos_to_abc_cmd(abc_script); + abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str()); + abc9_script = add_echos_to_abc9_cmd(abc9_script); - for (size_t i = 0; i+1 < abc_script.size(); i++) - if (abc_script[i] == ';' && abc_script[i+1] == ' ') - abc_script[i+1] = '\n'; + for (size_t i = 0; i+1 < abc9_script.size(); i++) + if (abc9_script[i] == ';' && abc9_script[i+1] == ' ') + abc9_script[i+1] = '\n'; FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt"); - fprintf(f, "%s\n", abc_script.c_str()); + fprintf(f, "%s\n", abc9_script.c_str()); fclose(f); if (dff_mode || !clk_str.empty()) @@ -420,7 +420,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // the expose operation -- remove them from PO/PI // and re-connecting them back together for (auto wire : module->wires()) { - auto it = wire->attributes.find(ID(abc_scc_break)); + auto it = wire->attributes.find(ID(abc9_scc_break)); if (it != wire->attributes.end()) { wire->attributes.erase(it); log_assert(wire->port_output); @@ -450,22 +450,22 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str()); #ifndef YOSYS_LINK_ABC - abc_output_filter filt(tempdir_name, show_tempdir); - int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); + abc9_output_filter filt(tempdir_name, show_tempdir); + int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1)); #else // These needs to be mutable, supposedly due to getopt - char *abc_argv[5]; + char *abc9_argv[5]; string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str()); - abc_argv[0] = strdup(exe_file.c_str()); - abc_argv[1] = strdup("-s"); - abc_argv[2] = strdup("-f"); - abc_argv[3] = strdup(tmp_script_name.c_str()); - abc_argv[4] = 0; - int ret = Abc_RealMain(4, abc_argv); - free(abc_argv[0]); - free(abc_argv[1]); - free(abc_argv[2]); - free(abc_argv[3]); + abc9_argv[0] = strdup(exe_file.c_str()); + abc9_argv[1] = strdup("-s"); + abc9_argv[2] = strdup("-f"); + abc9_argv[3] = strdup(tmp_script_name.c_str()); + abc9_argv[4] = 0; + int ret = Abc_RealMain(4, abc9_argv); + free(abc9_argv[0]); + free(abc9_argv[1]); + free(abc9_argv[2]); + free(abc9_argv[3]); #endif if (ret != 0) log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); @@ -513,7 +513,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri signal = std::move(bits); } - dict abc_box; + dict abc9_box; vector boxes; for (const auto &it : module->cells_) { auto cell = it.second; @@ -521,10 +521,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri module->remove(cell); continue; } - auto jt = abc_box.find(cell->type); - if (jt == abc_box.end()) { + auto jt = abc9_box.find(cell->type); + if (jt == abc9_box.end()) { RTLIL::Module* box_module = design->module(cell->type); - jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc_box_id)))).first; + jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first; } if (jt->second) boxes.emplace_back(cell); @@ -648,7 +648,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (!conn.second.is_wire()) continue; Wire *wire = conn.second.as_wire(); - if (!wire->get_bool_attribute(ID(abc_padding))) + if (!wire->get_bool_attribute(ID(abc9_padding))) continue; cell->unsetPort(conn.first); log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second)); @@ -827,17 +827,17 @@ struct Abc9Pass : public Pass { log(" if no -script parameter is given, the following scripts are used:\n"); log("\n"); log(" for -lut/-luts (only one LUT size):\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str()); + log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str()); log("\n"); log(" for -lut/-luts (different LUT sizes):\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str()); + log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str()); log("\n"); log(" -fast\n"); log(" use different default scripts that are slightly faster (at the cost\n"); log(" of output quality):\n"); log("\n"); log(" for -lut/-luts:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str()); + log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str()); log("\n"); log(" -D \n"); log(" set delay target. the string {D} in the default scripts above is\n"); @@ -1057,7 +1057,7 @@ struct Abc9Pass : public Pass { dict box_lookup; for (auto m : design->modules()) { - auto it = m->attributes.find(ID(abc_box_id)); + auto it = m->attributes.find(ID(abc9_box_id)); if (it == m->attributes.end()) continue; if (m->name.begins_with("$paramod")) @@ -1065,7 +1065,7 @@ struct Abc9Pass : public Pass { auto id = it->second.as_int(); auto r = box_lookup.insert(std::make_pair(id, m->name)); if (!r.second) - log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n", + log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n", log_id(m), id, log_id(r.first->second)); log_assert(r.second); @@ -1073,24 +1073,24 @@ struct Abc9Pass : public Pass { for (auto p : m->ports) { auto w = m->wire(p); log_assert(w); - if (w->attributes.count(ID(abc_carry))) { + if (w->attributes.count(ID(abc9_carry))) { if (w->port_input) { if (carry_in) - log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m)); + log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m)); carry_in = w; } else if (w->port_output) { if (carry_out) - log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m)); + log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m)); carry_out = w; } } } if (carry_in || carry_out) { if (carry_in && !carry_out) - log_error("Module '%s' contains an 'abc_carry' input port but no output port.\n", log_id(m)); + log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m)); if (!carry_in && carry_out) - log_error("Module '%s' contains an 'abc_carry' output port but no input port.\n", log_id(m)); + log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m)); // Make carry_in the last PI, and carry_out the last PO // since ABC requires it this way auto &ports = m->ports; @@ -1118,7 +1118,7 @@ struct Abc9Pass : public Pass { for (auto mod : design->selected_modules()) { - if (mod->attributes.count(ID(abc_box_id))) + if (mod->attributes.count(ID(abc9_box_id))) continue; if (mod->processes.size() > 0) { diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index b03da164c..5832d07ee 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -15,12 +15,12 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut)) EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc9_5g.box similarity index 96% rename from techlibs/ecp5/abc_5g.box rename to techlibs/ecp5/abc9_5g.box index a336b4a85..2bc945a54 100644 --- a/techlibs/ecp5/abc_5g.box +++ b/techlibs/ecp5/abc9_5g.box @@ -18,7 +18,7 @@ CCU2C 1 1 9 3 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) # Outputs: DO0, DO1, DO2, DO3 # name ID w/b ins outs -$__ABC_DPR16X4_COMB 2 0 8 4 +$__ABC9_DPR16X4_COMB 2 0 8 4 #A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 0 0 0 0 141 379 275 379 diff --git a/techlibs/ecp5/abc_5g.lut b/techlibs/ecp5/abc9_5g.lut similarity index 100% rename from techlibs/ecp5/abc_5g.lut rename to techlibs/ecp5/abc9_5g.lut diff --git a/techlibs/ecp5/abc_5g_nowide.lut b/techlibs/ecp5/abc9_5g_nowide.lut similarity index 100% rename from techlibs/ecp5/abc_5g_nowide.lut rename to techlibs/ecp5/abc9_5g_nowide.lut diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc9_map.v similarity index 89% rename from techlibs/ecp5/abc_map.v rename to techlibs/ecp5/abc9_map.v index ffd25f06d..d8d70f9f6 100644 --- a/techlibs/ecp5/abc_map.v +++ b/techlibs/ecp5/abc9_map.v @@ -20,5 +20,5 @@ module TRELLIS_DPR16X4 ( .RAD(RAD), .DO(\$DO ) ); - \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO)); + \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO)); endmodule diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v new file mode 100644 index 000000000..1dc8b5617 --- /dev/null +++ b/techlibs/ecp5/abc9_model.v @@ -0,0 +1,5 @@ +// --------------------------------------- + +(* abc9_box_id=2 *) +module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); +endmodule diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc9_unmap.v similarity index 52% rename from techlibs/ecp5/abc_unmap.v rename to techlibs/ecp5/abc9_unmap.v index d43cdd93f..9ae143c46 100644 --- a/techlibs/ecp5/abc_unmap.v +++ b/techlibs/ecp5/abc9_unmap.v @@ -1,5 +1,5 @@ // --------------------------------------- -module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); +module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); assign Y = A; endmodule diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v deleted file mode 100644 index 56a733b75..000000000 --- a/techlibs/ecp5/abc_model.v +++ /dev/null @@ -1,5 +0,0 @@ -// --------------------------------------- - -(* abc_box_id=2 *) -module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); -endmodule diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index db77dc127..f467218cc 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -9,19 +9,19 @@ module LUT4(input A, B, C, D, output Z); endmodule // --------------------------------------- -(* abc_box_id=4, lib_whitebox *) +(* abc9_box_id=4, lib_whitebox *) module L6MUX21 (input D0, D1, SD, output Z); assign Z = SD ? D1 : D0; endmodule // --------------------------------------- -(* abc_box_id=1, lib_whitebox *) +(* abc9_box_id=1, lib_whitebox *) module CCU2C( - (* abc_carry *) + (* abc9_carry *) input CIN, input A0, B0, C0, D0, A1, B1, C1, D1, output S0, S1, - (* abc_carry *) + (* abc9_carry *) output COUT ); parameter [15:0] INIT0 = 16'h0000; @@ -103,7 +103,7 @@ module TRELLIS_RAM16X2 ( endmodule // --------------------------------------- -(* abc_box_id=3, lib_whitebox *) +(* abc9_box_id=3, lib_whitebox *) module PFUMX (input ALUT, BLUT, C0, output Z); assign Z = C0 ? ALUT : BLUT; endmodule @@ -115,7 +115,7 @@ module TRELLIS_DPR16X4 ( input WRE, input WCK, input [3:0] RAD, - /* (* abc_arrival= *) */ + /* (* abc9_arrival= *) */ output [3:0] DO ); parameter WCKMUX = "WCK"; diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 67d2f483c..80aa1dbc5 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -307,16 +307,16 @@ struct SynthEcp5Pass : public ScriptPass } std::string techmap_args = "-map +/ecp5/latches_map.v"; if (abc9) - techmap_args += " -map +/ecp5/abc_map.v -max_iter 1"; + techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1"; run("techmap " + techmap_args); if (abc9) { - run("read_verilog -icells -lib +/ecp5/abc_model.v"); + run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) - run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200"); + run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200"); else - run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200"); - run("techmap -map +/ecp5/abc_unmap.v"); + run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200"); + run("techmap -map +/ecp5/abc9_unmap.v"); } else { if (nowidelut) run("abc -lut 4 -dress"); diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index 0fbca9034..3c33fcb06 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -28,13 +28,13 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_model.v)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.box)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.lut)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.box)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.lut)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.box)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.lut)) $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh)) $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh)) diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc9_hx.box similarity index 100% rename from techlibs/ice40/abc_hx.box rename to techlibs/ice40/abc9_hx.box diff --git a/techlibs/ice40/abc_hx.lut b/techlibs/ice40/abc9_hx.lut similarity index 100% rename from techlibs/ice40/abc_hx.lut rename to techlibs/ice40/abc9_hx.lut diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc9_lp.box similarity index 100% rename from techlibs/ice40/abc_lp.box rename to techlibs/ice40/abc9_lp.box diff --git a/techlibs/ice40/abc_lp.lut b/techlibs/ice40/abc9_lp.lut similarity index 100% rename from techlibs/ice40/abc_lp.lut rename to techlibs/ice40/abc9_lp.lut diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc9_model.v similarity index 79% rename from techlibs/ice40/abc_model.v rename to techlibs/ice40/abc9_model.v index fe31b8811..26cf6cc22 100644 --- a/techlibs/ice40/abc_model.v +++ b/techlibs/ice40/abc9_model.v @@ -1,10 +1,10 @@ -(* abc_box_id = 1, lib_whitebox *) +(* abc9_box_id = 1, lib_whitebox *) module \$__ICE40_CARRY_WRAPPER ( - (* abc_carry *) + (* abc9_carry *) output CO, output O, input A, B, - (* abc_carry *) + (* abc9_carry *) input CI, input I0, I3 ); diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc9_u.box similarity index 100% rename from techlibs/ice40/abc_u.box rename to techlibs/ice40/abc9_u.box diff --git a/techlibs/ice40/abc_u.lut b/techlibs/ice40/abc9_u.lut similarity index 100% rename from techlibs/ice40/abc_u.lut rename to techlibs/ice40/abc9_u.lut diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 16a893226..f9e79a61d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -2,9 +2,9 @@ `define SB_DFF_REG reg Q = 0 // `define SB_DFF_REG reg Q -`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif -`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif -`define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif +`define ABC9_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc9_arrival=TIME *) `endif +`define ABC9_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc9_arrival=TIME *) `endif +`define ABC9_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc9_arrival=TIME *) `endif // SiliconBlue IO Cells @@ -152,9 +152,9 @@ endmodule // Positive Edge SiliconBlue FF Cells module SB_DFF ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, D ); @@ -163,9 +163,9 @@ module SB_DFF ( endmodule module SB_DFFE ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, D ); @@ -175,9 +175,9 @@ module SB_DFFE ( endmodule module SB_DFFSR ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, R, D ); @@ -189,9 +189,9 @@ module SB_DFFSR ( endmodule module SB_DFFR ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, R, D ); @@ -203,9 +203,9 @@ module SB_DFFR ( endmodule module SB_DFFSS ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, S, D ); @@ -217,9 +217,9 @@ module SB_DFFSS ( endmodule module SB_DFFS ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, S, D ); @@ -231,9 +231,9 @@ module SB_DFFS ( endmodule module SB_DFFESR ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, R, D ); @@ -247,9 +247,9 @@ module SB_DFFESR ( endmodule module SB_DFFER ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, R, D ); @@ -261,9 +261,9 @@ module SB_DFFER ( endmodule module SB_DFFESS ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, S, D ); @@ -277,9 +277,9 @@ module SB_DFFESS ( endmodule module SB_DFFES ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, S, D ); @@ -293,9 +293,9 @@ endmodule // Negative Edge SiliconBlue FF Cells module SB_DFFN ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, D ); @@ -304,9 +304,9 @@ module SB_DFFN ( endmodule module SB_DFFNE ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, D ); @@ -316,9 +316,9 @@ module SB_DFFNE ( endmodule module SB_DFFNSR ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, R, D ); @@ -330,9 +330,9 @@ module SB_DFFNSR ( endmodule module SB_DFFNR ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, R, D ); @@ -344,9 +344,9 @@ module SB_DFFNR ( endmodule module SB_DFFNSS ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, S, D ); @@ -358,9 +358,9 @@ module SB_DFFNSS ( endmodule module SB_DFFNS ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, S, D ); @@ -372,9 +372,9 @@ module SB_DFFNS ( endmodule module SB_DFFNESR ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, R, D ); @@ -388,9 +388,9 @@ module SB_DFFNESR ( endmodule module SB_DFFNER ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, R, D ); @@ -402,9 +402,9 @@ module SB_DFFNER ( endmodule module SB_DFFNESS ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, S, D ); @@ -418,9 +418,9 @@ module SB_DFFNESS ( endmodule module SB_DFFNES ( - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output `SB_DFF_REG, input C, E, S, D ); @@ -434,9 +434,9 @@ endmodule // SiliconBlue RAM Cells module SB_RAM40_4K ( - `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 - `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 - `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 + `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 + `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 + `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 output [15:0] RDATA, input RCLK, RCLKE, RE, input [10:0] RADDR, @@ -605,9 +605,9 @@ module SB_RAM40_4K ( endmodule module SB_RAM40_4KNR ( - `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 - `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 - `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 + `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 + `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 + `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 output [15:0] RDATA, input RCLKN, RCLKE, RE, input [10:0] RADDR, @@ -673,9 +673,9 @@ module SB_RAM40_4KNR ( endmodule module SB_RAM40_4KNW ( - `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 - `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 - `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 + `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 + `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 + `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 output [15:0] RDATA, input RCLK, RCLKE, RE, input [10:0] RADDR, @@ -741,9 +741,9 @@ module SB_RAM40_4KNW ( endmodule module SB_RAM40_4KNRNW ( - `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 - `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 - `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 + `ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 + `ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 + `ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 output [15:0] RDATA, input RCLKN, RCLKE, RE, input [10:0] RADDR, @@ -813,9 +813,9 @@ endmodule module ICESTORM_LC ( input I0, I1, I2, I3, CIN, CLK, CEN, SR, output LO, - `ABC_ARRIVAL_HX(540) - `ABC_ARRIVAL_LP(796) - `ABC_ARRIVAL_U(1391) + `ABC9_ARRIVAL_HX(540) + `ABC9_ARRIVAL_LP(796) + `ABC9_ARRIVAL_U(1391) output O, output COUT ); @@ -1417,7 +1417,6 @@ module SB_MAC16 ( input ADDSUBTOP, ADDSUBBOT, input OHOLDTOP, OHOLDBOT, input CI, ACCUMCI, SIGNEXTIN, - //`ABC_ARRIVAL_U(1984) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 output [31:0] O, output CO, ACCUMCO, SIGNEXTOUT ); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2e4684c19..b66c6bf57 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -349,7 +349,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { - run("read_verilog -icells -lib +/ice40/abc_model.v"); + run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") wire_delay = 400; @@ -357,7 +357,7 @@ struct SynthIce40Pass : public ScriptPass wire_delay = 750; else wire_delay = 250; - run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); } else run(abc + " -dress -lut 4", "(skip if -noabc)"); diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index ae82311a9..0ae67d9e7 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -44,12 +44,12 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.box)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.lut)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7_nowide.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc9_map.v similarity index 88% rename from techlibs/xilinx/abc_map.v rename to techlibs/xilinx/abc9_map.v index e4976092c..0eac08f3f 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -39,8 +39,8 @@ module RAM32X1D ( .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4) ); - \$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO)); - \$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO)); + \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO)); + \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO)); endmodule module RAM64X1D ( @@ -62,8 +62,8 @@ module RAM64X1D ( .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5) ); - \$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO)); - \$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO)); + \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO)); + \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO)); endmodule module RAM128X1D ( @@ -84,8 +84,8 @@ module RAM128X1D ( .A(A), .DPRA(DPRA) ); - \$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO)); - \$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO)); + \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO)); + \$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO)); endmodule module SRL16E ( @@ -101,7 +101,7 @@ module SRL16E ( .Q(\$Q ), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D) ); - \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q)); + \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q)); endmodule module SRLC32E ( @@ -119,7 +119,7 @@ module SRLC32E ( .Q(\$Q ), .Q31(Q31), .A(A), .CE(CE), .CLK(CLK), .D(D) ); - \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q)); + \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q)); endmodule module DSP48E1 ( @@ -308,15 +308,15 @@ __CELL__ #( if (AREG == 0 && MREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); + \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); + \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); + \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0) assign iD = D; else if (techmap_guard) @@ -327,27 +327,27 @@ __CELL__ #( assign pAD = 1'bx; if (PREG == 0) begin if (MREG == 1) - \$__ABC_REG rM (.Q(pM)); + \$__ABC9_REG rM (.Q(pM)); else assign pM = 1'bx; assign pP = 1'bx; end else begin assign pM = 1'bx; - \$__ABC_REG rP (.Q(pP)); + \$__ABC9_REG rP (.Q(pP)); end if (MREG == 0 && PREG == 0) assign mP = oP, mPCOUT = oPCOUT; else assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC_DSP48E1_MULT_P_MUX muxP ( + \$__ABC9_DSP48E1_MULT_P_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); - \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( + \$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC_DSP48E1_MULT ) + `DSP48E1_INST(\$__ABC9_DSP48E1_MULT ) end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin // Disconnect the A-input if MREG is enabled, since @@ -355,26 +355,26 @@ __CELL__ #( if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); + \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); + \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); + \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0 && ADREG == 0) assign iD = D, pD = 1'bx; else - \$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD)); + \$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD)); if (PREG == 0) begin if (MREG == 1) begin assign pAD = 1'bx; - \$__ABC_REG rM (.Q(pM)); + \$__ABC9_REG rM (.Q(pM)); end else begin if (ADREG == 1) - \$__ABC_REG rAD (.Q(pAD)); + \$__ABC9_REG rAD (.Q(pAD)); else assign pAD = 1'bx; assign pM = 1'bx; @@ -382,21 +382,21 @@ __CELL__ #( assign pP = 1'bx; end else begin assign pAD = 1'bx, pM = 1'bx; - \$__ABC_REG rP (.Q(pP)); + \$__ABC9_REG rP (.Q(pP)); end if (MREG == 0 && PREG == 0) assign mP = oP, mPCOUT = oPCOUT; else assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP ( + \$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); - \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( + \$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT ) + `DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT ) end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin // Disconnect the A-input if MREG is enabled, since @@ -404,15 +404,15 @@ __CELL__ #( if (AREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); + \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); + \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); + \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (DREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); assign pD = 1'bx; @@ -423,7 +423,7 @@ __CELL__ #( $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); assign pM = 1'bx; if (PREG == 1) - \$__ABC_REG rP (.Q(pP)); + \$__ABC9_REG rP (.Q(pP)); else assign pP = 1'bx; @@ -431,14 +431,14 @@ __CELL__ #( assign mP = oP, mPCOUT = oPCOUT; else assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC_DSP48E1_P_MUX muxP ( + \$__ABC9_DSP48E1_P_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); - \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT ( + \$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC_DSP48E1 ) + `DSP48E1_INST(\$__ABC9_DSP48E1 ) end else $error("Invalid DSP48E1 configuration"); diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc9_model.v similarity index 83% rename from techlibs/xilinx/abc_model.v rename to techlibs/xilinx/abc9_model.v index f19235a27..8c8e1556c 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -24,7 +24,7 @@ // Necessary to make these an atomic unit so that // ABC cannot optimise just one of the MUXF7 away // and expect to save on its delay -(* abc_box_id = 3, lib_whitebox *) +(* abc9_box_id = 3, lib_whitebox *) module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); assign O = S1 ? (S0 ? I3 : I2) : (S0 ? I1 : I0); @@ -36,32 +36,32 @@ endmodule // is only committed on the next clock edge). // To model the combinatorial path, such cells have to be split // into comb and seq parts, with this box modelling only the former. -(* abc_box_id=2000 *) -module \$__ABC_LUT6 (input A, input [5:0] S, output Y); +(* abc9_box_id=2000 *) +module \$__ABC9_LUT6 (input A, input [5:0] S, output Y); endmodule // Box to emulate comb/seq behaviour of RAMD128 -(* abc_box_id=2001 *) -module \$__ABC_LUT7 (input A, input [6:0] S, output Y); +(* abc9_box_id=2001 *) +module \$__ABC9_LUT7 (input A, input [6:0] S, output Y); endmodule // Modules used to model the comb/seq behaviour of DSP48E1 -// With abc_map.v responsible for splicing the below modules +// With abc9_map.v responsible for splicing the below modules // between the combinatorial DSP48E1 box (e.g. disconnecting // A when AREG, MREG or PREG is enabled and splicing in the -// "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below) +// "$__ABC9_DSP48E1_REG" blackbox as "REG" in the diagram below) // this acts to first disables the combinatorial path (as there // is no connectivity through REG), and secondly, since this is // blackbox a new PI will be introduced with an arrival time of // zero. -// Note: Since these "$__ABC_DSP48E1_REG" modules are of a +// Note: Since these "$__ABC9_DSP48E1_REG" modules are of a // sequential nature, they are not passed as a box to ABC and // (desirably) represented as PO/PIs. // // At the DSP output, we place a blackbox mux ("M" in the diagram // below) to capture the fact that the critical-path could come // from any one of its inputs. -// In contrast to "REG", the "$__ABC_DSP48E1_*_MUX" modules are +// In contrast to "REG", the "$__ABC9_DSP48E1_*_MUX" modules are // combinatorial blackboxes that do get passed to ABC. // The propagation delay through this box (specified in the box // file) captures the arrival time of the register (i.e. @@ -90,18 +90,18 @@ endmodule // B >>------| | // +---------+ // -`define ABC_DSP48E1_MUX(__NAME__) """ +`define ABC9_DSP48E1_MUX(__NAME__) """ module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O); endmodule """ -(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) -(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX ) -(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX ) -(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX ) -(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX ) -(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) +(* abc9_box_id=2100 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_P_MUX ) +(* abc9_box_id=2101 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_PCOUT_MUX ) +(* abc9_box_id=2102 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_P_MUX ) +(* abc9_box_id=2103 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX ) +(* abc9_box_id=2104 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_P_MUX ) +(* abc9_box_id=2105 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_PCOUT_MUX ) -`define ABC_DSP48E1(__NAME__) """ +`define ABC9_DSP48E1(__NAME__) """ module __NAME__ ( output [29:0] ACOUT, output [17:0] BCOUT, @@ -185,6 +185,6 @@ module __NAME__ ( parameter [6:0] IS_OPMODE_INVERTED = 7'b0; endmodule """ -(* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT ) -(* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT ) -(* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 ) +(* abc9_box_id=3000 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT ) +(* abc9_box_id=3001 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT_DPORT ) +(* abc9_box_id=3002 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1 ) diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc9_unmap.v similarity index 92% rename from techlibs/xilinx/abc_unmap.v rename to techlibs/xilinx/abc9_unmap.v index 8bd0579ed..ad6469702 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -20,19 +20,19 @@ // ============================================================================ -module \$__ABC_LUT6 (input A, input [5:0] S, output Y); +module \$__ABC9_LUT6 (input A, input [5:0] S, output Y); assign Y = A; endmodule -module \$__ABC_LUT7 (input A, input [6:0] S, output Y); +module \$__ABC9_LUT7 (input A, input [6:0] S, output Y); assign Y = A; endmodule -module \$__ABC_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q); +module \$__ABC9_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q); parameter WIDTH = 1; assign O = I; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) -module \$__ABC_DSP48E1_MUX ( +(* techmap_celltype = "$__ABC9_DSP48E1_MULT_P_MUX $__ABC9_DSP48E1_MULT_PCOUT_MUX $__ABC9_DSP48E1_MULT_DPORT_P_MUX $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC9_DSP48E1_P_MUX $__ABC9_DSP48E1_PCOUT_MUX" *) +module \$__ABC9_DSP48E1_MUX ( input Aq, Bq, Cq, Dq, ADq, input [47:0] I, input Mq, @@ -43,8 +43,8 @@ module \$__ABC_DSP48E1_MUX ( assign O = I; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *) -module \$__ABC_DSP48E1 ( +(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *) +module \$__ABC9_DSP48E1 ( (* techmap_autopurge *) output [29:0] ACOUT, (* techmap_autopurge *) output [17:0] BCOUT, (* techmap_autopurge *) output reg CARRYCASCOUT, diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc9_xc7.box similarity index 99% rename from techlibs/xilinx/abc_xc7.box rename to techlibs/xilinx/abc9_xc7.box index 3da3d1b3f..774388d49 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -50,18 +50,18 @@ CARRY4 4 1 10 8 # into comb and seq parts, with this box modelling only the former. # Inputs: A S0 S1 S2 S3 S4 S5 # Outputs: Y -$__ABC_LUT6 2000 0 7 1 +$__ABC9_LUT6 2000 0 7 1 0 642 631 472 407 238 127 # SLICEM/A6LUT + F7BMUX # Box to emulate comb/seq behaviour of RAMD128 # Inputs: A S0 S1 S2 S3 S4 S5 S6 # Outputs: DPO SPO -$__ABC_LUT7 2001 0 8 1 +$__ABC9_LUT7 2001 0 8 1 0 1047 1036 877 812 643 532 478 # Boxes used to represent the comb/seq behaviour of DSP48E1 -# With abc_map.v responsible for disconnecting inputs to +# With abc9_map.v responsible for disconnecting inputs to # the combinatorial DSP48E1 model by a register (e.g. # disconnecting A when AREG, MREG or PREG is enabled) # this mux captures the existence of a replacement path @@ -70,7 +70,7 @@ $__ABC_LUT7 2001 0 8 1 # the mux at zero time, the combinatorial delay through # these muxes thus represents the clock-to-q delay at # P/PCOUT. -$__ABC_DSP48E1_MULT_P_MUX 2100 0 103 48 +$__ABC9_DSP48E1_MULT_P_MUX 2100 0 103 48 # A AD B C D I M P Pq 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 @@ -120,7 +120,7 @@ $__ABC_DSP48E1_MULT_P_MUX 2100 0 103 48 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -$__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48 +$__ABC9_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48 # A AD B C D I M P Pq 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 @@ -170,7 +170,7 @@ $__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 103 48 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 3098 - 2960 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 -$__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48 +$__ABC9_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48 # A AD B C D I M P Pq 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 @@ -220,7 +220,7 @@ $__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 103 48 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 3935 2958 2813 1687 3908 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48 +$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48 # A AD B C D I M P Pq 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 @@ -270,7 +270,7 @@ $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 103 48 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 4083 2859 2960 1835 4056 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 -$__ABC_DSP48E1_P_MUX 2104 0 103 48 +$__ABC9_DSP48E1_P_MUX 2104 0 103 48 # A AD B C D I M P Pq 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 @@ -320,7 +320,7 @@ $__ABC_DSP48E1_P_MUX 2104 0 103 48 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 1632 - 1616 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -$__ABC_DSP48E1_PCOUT_MUX 2105 0 103 48 +$__ABC9_DSP48E1_PCOUT_MUX 2105 0 103 48 # A AD B C D I M P Pq 1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 @@ -371,7 +371,7 @@ $__ABC_DSP48E1_PCOUT_MUX 2105 0 103 48 1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 1780 - 1765 1835 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 -$__ABC_DSP48E1_MULT 3000 0 263 154 +$__ABC9_DSP48E1_MULT 3000 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 - @@ -635,7 +635,7 @@ $__ABC_DSP48E1_MULT 3000 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -$__ABC_DSP48E1_MULT_DPORT 3001 0 263 154 +$__ABC9_DSP48E1_MULT_DPORT 3001 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 - @@ -899,7 +899,7 @@ $__ABC_DSP48E1_MULT_DPORT 3001 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -$__ABC_DSP48E1 3002 0 263 154 +$__ABC9_DSP48E1 3002 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 - diff --git a/techlibs/xilinx/abc_xc7.lut b/techlibs/xilinx/abc9_xc7.lut similarity index 100% rename from techlibs/xilinx/abc_xc7.lut rename to techlibs/xilinx/abc9_xc7.lut diff --git a/techlibs/xilinx/abc_xc7_nowide.lut b/techlibs/xilinx/abc9_xc7_nowide.lut similarity index 100% rename from techlibs/xilinx/abc_xc7_nowide.lut rename to techlibs/xilinx/abc9_xc7_nowide.lut diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 258999f18..28cd208cd 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -184,12 +184,12 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule -(* abc_box_id = 1, lib_whitebox *) +(* abc9_box_id = 1, lib_whitebox *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 2, lib_whitebox *) +(* abc9_box_id = 2, lib_whitebox *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule @@ -198,12 +198,12 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 4, lib_whitebox *) +(* abc9_box_id = 4, lib_whitebox *) module CARRY4( - (* abc_carry *) + (* abc9_carry *) output [3:0] CO, output [3:0] O, - (* abc_carry *) + (* abc9_carry *) input CI, input CYINIT, input [3:0] DI, S @@ -241,7 +241,7 @@ endmodule // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 module FDRE ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -264,7 +264,7 @@ module FDRE ( endmodule module FDSE ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -287,7 +287,7 @@ module FDSE ( endmodule module FDCE ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -312,7 +312,7 @@ module FDCE ( endmodule module FDPE ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) @@ -337,7 +337,7 @@ module FDPE ( endmodule module FDRE_1 ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, @@ -349,7 +349,7 @@ module FDRE_1 ( endmodule module FDSE_1 ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, @@ -361,7 +361,7 @@ module FDSE_1 ( endmodule module FDCE_1 ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, @@ -373,7 +373,7 @@ module FDCE_1 ( endmodule module FDPE_1 ( - (* abc_arrival=303 *) + (* abc9_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, @@ -430,7 +430,7 @@ endmodule module RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) + (* abc9_arrival=1153 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -453,7 +453,7 @@ endmodule module RAM64X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) + (* abc9_arrival=1153 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -476,7 +476,7 @@ endmodule module RAM128X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) + (* abc9_arrival=1153 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -496,7 +496,7 @@ endmodule module SRL16E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) + (* abc9_arrival=1472 *) output Q, input A0, A1, A2, A3, CE, (* clkbuf_sink *) @@ -544,9 +544,9 @@ endmodule module SRLC32E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) + (* abc9_arrival=1472 *) output Q, - (* abc_arrival=1114 *) + (* abc9_arrival=1114 *) output Q31, input [4:0] A, input CE, diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7085214de..5c2b1402c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -474,13 +474,14 @@ struct SynthXilinxPass : public ScriptPass run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')"); else if (abc9) { if (family != "xc7") - log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); - run("techmap -map +/xilinx/abc_map.v -max_iter 1"); - run("read_verilog -icells -lib +/xilinx/abc_model.v"); + log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " + "will use timing for 'xc7' instead.\n", family.c_str()); + run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); + run("read_verilog -icells -lib +/xilinx/abc9_model.v"); if (nowidelut) - run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + run("abc9 -lut +/xilinx/abc9_xc7_nowide.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); else - run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + run("abc9 -lut +/xilinx/abc9_xc7.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); } else { if (nowidelut) @@ -498,7 +499,7 @@ struct SynthXilinxPass : public ScriptPass if (help_mode) techmap_args += " [-map " + ff_map_file + "]"; else if (abc9) - techmap_args += " -map +/xilinx/abc_unmap.v"; + techmap_args += " -map +/xilinx/abc9_unmap.v"; else techmap_args += " -map " + ff_map_file; run("techmap " + techmap_args); diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v index 041d6b54f..3c323a90b 100644 --- a/techlibs/xilinx/xc6s_brams_bb.v +++ b/techlibs/xilinx/xc6s_brams_bb.v @@ -19,9 +19,13 @@ module RAMB8BWER ( input [1:0] WEAWEL, input [1:0] WEBWEU, + /* (* abc9_arrival= *) */ output [15:0] DOADO, + /* (* abc9_arrival= *) */ output [15:0] DOBDO, + /* (* abc9_arrival= *) */ output [1:0] DOPADOP, + /* (* abc9_arrival= *) */ output [1:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -109,9 +113,13 @@ module RAMB16BWER ( input [3:0] WEA, input [3:0] WEB, + /* (* abc9_arrival= *) */ output [31:0] DOA, + /* (* abc9_arrival= *) */ output [31:0] DOB, + /* (* abc9_arrival= *) */ output [3:0] DOPA, + /* (* abc9_arrival= *) */ output [3:0] DOPB ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index a28ba5b14..c374f26b9 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -31,13 +31,13 @@ module RAMB18E1 ( input [1:0] WEA, input [3:0] WEBWE, - (* abc_arrival=2454 *) + (* abc9_arrival=2454 *) output [15:0] DOADO, - (* abc_arrival=2454 *) + (* abc9_arrival=2454 *) output [15:0] DOBDO, - (* abc_arrival=2454 *) + (* abc9_arrival=2454 *) output [1:0] DOPADOP, - (* abc_arrival=2454 *) + (* abc9_arrival=2454 *) output [1:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -169,13 +169,13 @@ module RAMB36E1 ( input [3:0] WEA, input [7:0] WEBWE, - (* abc_arrival=2454 *) + (* abc9_arrival=2454 *) output [31:0] DOADO, - (* abc_arrival=2454 *) + (* abc9_arrival=2454 *) output [31:0] DOBDO, - (* abc_arrival=2454 *) + (* abc9_arrival=2454 *) output [3:0] DOPADOP, - (* abc_arrival=2454 *) + (* abc9_arrival=2454 *) output [3:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; From 279fd22ddfe44a9ddd6504134d1029f6b7649149 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 13:31:33 -0700 Subject: [PATCH 059/123] Add Const::{begin,end,empty}() --- kernel/rtlil.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c08653b65..e5b24cc02 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -609,8 +609,11 @@ struct RTLIL::Const std::string decode_string() const; inline int size() const { return bits.size(); } + inline bool empty() const { return bits.empty(); } inline RTLIL::State &operator[](int index) { return bits.at(index); } inline const RTLIL::State &operator[](int index) const { return bits.at(index); } + inline decltype(bits)::iterator begin() { return bits.begin(); } + inline decltype(bits)::iterator end() { return bits.end(); } bool is_fully_zero() const; bool is_fully_ones() const; From 6bf7114bbd4075c2761a478406e02d4b23742aab Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 16:45:36 -0700 Subject: [PATCH 060/123] Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again --- kernel/rtlil.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ded1cd60e..bd2fd91a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const if (width_ != other.width_) return false; + // Without this, SigSpec() == SigSpec(State::S0, 0) will fail + // since the RHS will contain one SigChunk of width 0 causing + // the size check below to fail + if (width_ == 0) + return true; + pack(); other.pack(); From 74ef8feeaf63b41e8948ce09d40420ccdb48957a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 16:46:15 -0700 Subject: [PATCH 061/123] Fix xilinx_dsp for unsigned extensions --- passes/pmgen/xilinx_dsp.pmg | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 3d0b1f2c3..4e174e753 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -277,7 +277,9 @@ match postAdd index port(postAdd, AB)[0] === sigP[0] filter GetSize(port(postAdd, AB)) >= GetSize(sigP) filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP - filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) + // Check that remainder of AB is a sign-extension + define AB_SIGNED (param(postAdd, AB == \A ? \A_SIGNED : \B_SIGNED).as_bool()) + filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(AB_SIGNED ? sigP[GetSize(sigP)-1] : State::S0, GetSize(port(postAdd, AB))-GetSize(sigP)) set postAddAB AB optional endmatch From 9c238118395ceae76bff59fe1028d43768c79fed Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 17:26:42 -0700 Subject: [PATCH 062/123] Remove DSP48E1 from *_cells_xtra.v --- techlibs/xilinx/cells_xtra.py | 4 +- techlibs/xilinx/xc6v_cells_xtra.v | 88 ------------------------------- techlibs/xilinx/xc7_cells_xtra.v | 88 ------------------------------- 3 files changed, 2 insertions(+), 178 deletions(-) diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 13dbc0e14..ee20ae992 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -137,7 +137,7 @@ XC6V_CELLS = [ Cell('SYSMON'), # Arithmetic functions. - Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), + #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Clock components. # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), @@ -264,7 +264,7 @@ XC7_CELLS = [ Cell('XADC'), # Arithmetic functions. - Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), + #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Clock components. # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v index b228e404d..d9e06eae2 100644 --- a/techlibs/xilinx/xc6v_cells_xtra.v +++ b/techlibs/xilinx/xc6v_cells_xtra.v @@ -647,94 +647,6 @@ module SYSMON (...); input [6:0] DADDR; endmodule -module DSP48E1 (...); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - output [29:0] ACOUT; - output [17:0] BCOUT; - output CARRYCASCOUT; - output [3:0] CARRYOUT; - output MULTSIGNOUT; - output OVERFLOW; - output [47:0] P; - output PATTERNBDETECT; - output PATTERNDETECT; - output [47:0] PCOUT; - output UNDERFLOW; - input [29:0] A; - input [29:0] ACIN; - (* invertible_pin = "IS_ALUMODE_INVERTED" *) - input [3:0] ALUMODE; - input [17:0] B; - input [17:0] BCIN; - input [47:0] C; - input CARRYCASCIN; - (* invertible_pin = "IS_CARRYIN_INVERTED" *) - input CARRYIN; - input [2:0] CARRYINSEL; - input CEA1; - input CEA2; - input CEAD; - input CEALUMODE; - input CEB1; - input CEB2; - input CEC; - input CECARRYIN; - input CECTRL; - input CED; - input CEINMODE; - input CEM; - input CEP; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [24:0] D; - (* invertible_pin = "IS_INMODE_INVERTED" *) - input [4:0] INMODE; - input MULTSIGNIN; - (* invertible_pin = "IS_OPMODE_INVERTED" *) - input [6:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTALLCARRYIN; - input RSTALUMODE; - input RSTB; - input RSTC; - input RSTCTRL; - input RSTD; - input RSTINMODE; - input RSTM; - input RSTP; -endmodule - module BUFGCE (...); parameter CE_TYPE = "SYNC"; parameter [0:0] IS_CE_INVERTED = 1'b0; diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v index 0d16f81c3..f36e4baa2 100644 --- a/techlibs/xilinx/xc7_cells_xtra.v +++ b/techlibs/xilinx/xc7_cells_xtra.v @@ -3376,94 +3376,6 @@ module XADC (...); input [6:0] DADDR; endmodule -module DSP48E1 (...); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - output [29:0] ACOUT; - output [17:0] BCOUT; - output CARRYCASCOUT; - output [3:0] CARRYOUT; - output MULTSIGNOUT; - output OVERFLOW; - output [47:0] P; - output PATTERNBDETECT; - output PATTERNDETECT; - output [47:0] PCOUT; - output UNDERFLOW; - input [29:0] A; - input [29:0] ACIN; - (* invertible_pin = "IS_ALUMODE_INVERTED" *) - input [3:0] ALUMODE; - input [17:0] B; - input [17:0] BCIN; - input [47:0] C; - input CARRYCASCIN; - (* invertible_pin = "IS_CARRYIN_INVERTED" *) - input CARRYIN; - input [2:0] CARRYINSEL; - input CEA1; - input CEA2; - input CEAD; - input CEALUMODE; - input CEB1; - input CEB2; - input CEC; - input CECARRYIN; - input CECTRL; - input CED; - input CEINMODE; - input CEM; - input CEP; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [24:0] D; - (* invertible_pin = "IS_INMODE_INVERTED" *) - input [4:0] INMODE; - input MULTSIGNIN; - (* invertible_pin = "IS_OPMODE_INVERTED" *) - input [6:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTALLCARRYIN; - input RSTALUMODE; - input RSTB; - input RSTC; - input RSTCTRL; - input RSTD; - input RSTINMODE; - input RSTM; - input RSTP; -endmodule - module BUFGCE (...); parameter CE_TYPE = "SYNC"; parameter [0:0] IS_CE_INVERTED = 1'b0; From 0acc51c3d82f65f73fa9e475c6fc41beabd925a6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 17:35:43 -0700 Subject: [PATCH 063/123] Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` --- passes/techmap/abc9.cc | 16 +++++++++++++--- techlibs/xilinx/synth_xilinx.cc | 8 ++++++-- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 09d6e9670..8932e860a 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -247,7 +247,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, bool show_tempdir, std::string box_file, std::string lut_file, - std::string wire_delay, const dict &box_lookup + std::string wire_delay, const dict &box_lookup, bool nomfs ) { module = current_module; @@ -346,6 +346,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos)) abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3); + if (nomfs) + for (size_t pos = abc_script.find("&mfs"); pos != std::string::npos; pos = abc_script.find("&mfs", pos)) + abc_script = abc_script.erase(pos, strlen("&mfs")); + + abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str()); abc_script = add_echos_to_abc_cmd(abc_script); @@ -921,6 +926,7 @@ struct Abc9Pass : public Pass { std::string delay_target, lutin_shared = "-S 1", wire_delay; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false; + bool nomfs = false; vector lut_costs; markgroups = false; @@ -1043,6 +1049,10 @@ struct Abc9Pass : public Pass { wire_delay = "-W " + args[++argidx]; continue; } + if (arg == "-nomfs") { + nomfs = true; + continue; + } break; } extra_args(args, argidx, design); @@ -1131,7 +1141,7 @@ struct Abc9Pass : public Pass { if (!dff_mode || !clk_str.empty()) { abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, wire_delay, box_lookup); + box_file, lut_file, wire_delay, box_lookup, nomfs); continue; } @@ -1277,7 +1287,7 @@ struct Abc9Pass : public Pass { en_sig = assign_map(std::get<3>(it.first)); abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, wire_delay, box_lookup); + box_file, lut_file, wire_delay, box_lookup, nomfs); assign_map.set(mod); } } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7085214de..1cddd2a92 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -477,10 +477,14 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); run("techmap -map +/xilinx/abc_map.v -max_iter 1"); run("read_verilog -icells -lib +/xilinx/abc_model.v"); + std::string abc9_opts = " -box +/xilinx/abc_xc7.box"; + abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); + abc9_opts += " -nomfs"; if (nowidelut) - run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut"; else - run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc_xc7.lut"; + run("abc9" + abc9_opts); } else { if (nowidelut) From b47bb5c8100bf24c7075dc322f201779eda280b7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 21:43:15 -0700 Subject: [PATCH 064/123] Fix typo in check_label() --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1cddd2a92..41429b338 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -339,7 +339,7 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); } - if (check_label("map_dsp"), "(skip if '-nodsp')") { + if (check_label("map_dsp", "(skip if '-nodsp')")) { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " From cf82b38478e598c915d14d595b554fc122034850 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 12:40:34 -0700 Subject: [PATCH 065/123] Add comments for xilinx_dsp --- passes/pmgen/xilinx_dsp.cc | 14 +++-- passes/pmgen/xilinx_dsp.pmg | 93 +++++++++++++++++++++++++++++++- passes/pmgen/xilinx_dsp_CREG.pmg | 33 +++++++++++- 3 files changed, 134 insertions(+), 6 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 11c7e5ea8..489887207 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -608,8 +608,13 @@ struct XilinxDspPass : public Pass { extra_args(args, argidx, design); for (auto module : design->selected_modules()) { + // Experimental feature: pack $add/$sub cells with + // (* use_dsp48="simd" *) into DSP48E1's using its + // SIMD feature xilinx_simd_pack(module, module->selected_cells()); + // Match for all features ([ABDMP][12]?REG, pre-adder, + // (post-adder, pattern detector, etc.) except for CREG { xilinx_dsp_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_pack(xilinx_dsp_pack); @@ -618,14 +623,17 @@ struct XilinxDspPass : public Pass { // is no guarantee that the cell ordering corresponds // to the "expected" case (i.e. the order in which // they appear in the source) thus the possiblity - // existed that a register got packed as CREG into a + // existed that a register got packed as a CREG into a // downstream DSP that should have otherwise been a - // PREG of an upstream DSP that had not been pattern - // matched yet + // PREG of an upstream DSP that had not been visited + // yet { xilinx_dsp_CREG_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_packC(xilinx_dsp_packC); } + // Lastly, identify and utilise PCOUT -> PCIN, + // ACOUT -> ACIN, and BCOUT-> BCIN dedicated cascade + // chains { xilinx_dsp_cascade_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_cascade(); diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 4e174e753..bcf966a8a 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -1,3 +1,53 @@ +// This file describes the main pattern matcher setup (of three total) that +// forms the `xilinx_dsp` pass described in xilinx_dsp.cc +// At a high level, it works as follows: +// ( 1) Starting from a DSP48E1 cell +// ( 2) Match the driver of the 'A' input to a possible $dff cell (ADREG) +// (attached to at most two $mux cells that implement clock-enable or +// reset functionality, using a subpattern discussed below) +// If ADREG matched, treat 'A' input as input of ADREG +// ( 3) Match the driver of the 'A' and 'D' inputs for a possible $add cell +// (pre-adder) +// ( 4) If pre-adder was present, find match 'A' input for A2REG +// If pre-adder was not present, move ADREG to A2REG +// If A2REG, then match 'A' input for A1REG +// ( 5) Match 'B' input for B2REG +// If B2REG, then match 'B' input for B1REG +// ( 6) Match 'D' input for DREG +// ( 7) Match 'P' output that exclusively drives an MREG +// ( 8) Match 'P' output that exclusively drives one of two inputs to an $add +// cell (post-adder). +// The other input to the adder is assumed to come in from the 'C' input +// (note: 'P' -> 'C' connections that exist for accumulators are +// recognised in xilinx_dsp.cc). +// ( 9) Match 'P' output that exclusively drives a PREG +// (10) If post-adder and PREG both present, match for a $mux cell driving +// the 'C' input, where one of the $mux's inputs is the PREG output. +// This indicates an accumulator situation, and one where a $mux exists +// to override the accumulated value: +// +--------------------------------+ +// | ____ | +// +--| \ | +// |$mux|-+ | +// 'C' ---|____/ | | +// | /-------\ +----+ | +// +----+ +-| post- |___|PREG|---+ 'P' +// |MREG|------ | adder | +----+ +// +----+ \-------/ +// (11) If PREG present, match for a greater-than-or-equal $ge cell attached +// to the 'P' output where it is compared to a constant that is a +// power-of-2: e.g. `assign overflow = (PREG >= 2**40);` +// In this scenario, the pattern detector functionality of a DSP48E1 can +// to implement this function +// Notes: +// - The intention of this pattern matcher is for it to be compatible with +// DSP48E1 cells inferred from multiply operations by Yosys, as well as for +// user instantiations that may already contain the cells being packed... +// (though the latter is currently untested) +// - Since the $dff-with-clock-enable-or-reset-mux pattern is used for each +// *REG match, it has been factored out into two subpatterns: in_dffe +// out_dffe located at the bottom of this file + pattern xilinx_dsp_pack state clock @@ -5,12 +55,11 @@ state sigA sigB sigC sigD sigM sigP state postAddAB postAddMuxAB state ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffDcepol ffMcepol ffPcepol state ffArstpol ffADrstpol ffBrstpol ffDrstpol ffMrstpol ffPrstpol - state ffAD ffADcemux ffADrstmux ffA1 ffA1cemux ffA1rstmux ffA2 ffA2cemux ffA2rstmux state ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux state ffD ffDcemux ffDrstmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux -// subpattern +// Variables used for subpatterns state argQ argD state ffcepol ffrstpol state ffoffset @@ -19,6 +68,7 @@ udata dffclock udata dff dffcemux dffrstmux udata dffcepol dffrstpol +// (1) Starting from a DSP48E1 cell match dsp select dsp->type.in(\DSP48E1) endmatch @@ -53,6 +103,7 @@ code sigA sigB sigC sigD sigM clock } else sigM = P; + // TODO: Check if necessary // This sigM could have no users if downstream $add // is narrower than $mul result, for example if (sigM.empty()) @@ -61,6 +112,10 @@ code sigA sigB sigC sigD sigM clock clock = port(dsp, \CLK, SigBit()); endcode +// (2) Match the driver of the 'A' input to a possible $dff cell (ADREG) +// (attached to at most two $mux cells that implement clock-enable or +// reset functionality, using a subpattern discussed above) +// If matched, treat 'A' input as input of ADREG code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock if (param(dsp, \ADREG).as_int() == 0) { argQ = sigA; @@ -81,6 +136,8 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock } endcode +// (3) Match the driver of the 'A' and 'D' inputs for a possible $add cell +// (pre-adder) match preAdd if sigD.empty() || sigD.is_fully_zero() // Ensure that preAdder not already used @@ -103,6 +160,7 @@ match preAdd endmatch code sigA sigD + // TODO: Check if this is necessary? if (preAdd) { sigA = port(preAdd, \A); sigD = port(preAdd, \B); @@ -111,6 +169,9 @@ code sigA sigD } endcode +// (4) If pre-adder was present, find match 'A' input for A2REG +// If pre-adder was not present, move ADREG to A2REG +// Then match 'A' input for A1REG code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cemux ffA2rstmux ffA2cepol ffArstpol ffA1 ffA1cemux ffA1rstmux ffA1cepol // Only search for ffA2 if there was a pre-adder // (otherwise ffA2 would have been matched as ffAD) @@ -173,6 +234,8 @@ ffA1_end: ; } endcode +// (5) Match 'B' input for B2REG +// If B2REG, then match 'B' input for B1REG code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock ffB1 ffB1cemux ffB1rstmux ffB1cepol if (param(dsp, \BREG).as_int() == 0) { argQ = sigB; @@ -222,6 +285,7 @@ ffB1_end: ; } endcode +// (6) Match 'D' input for DREG code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock if (param(dsp, \DREG).as_int() == 0) { argQ = sigD; @@ -242,6 +306,7 @@ code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock } endcode +// (7) Match 'P' output that exclusively drives an MREG code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) { argD = sigM; @@ -263,6 +328,11 @@ code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock sigP = sigM; endcode +// (8) Match 'P' output that exclusively drives one of two inputs to an $add +// cell (post-adder). +// The other input to the adder is assumed to come in from the 'C' input +// (note: 'P' -> 'C' connections that exist for accumulators are +// recognised in xilinx_dsp.cc). match postAdd // Ensure that Z mux is not already used if port(dsp, \OPMODE, SigSpec()).extract(4,3).is_fully_zero() @@ -291,6 +361,7 @@ code sigC sigP } endcode +// (9) Match 'P' output that exclusively drives a PREG code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock if (param(dsp, \PREG).as_int() == 0) { int users = 2; @@ -316,6 +387,19 @@ code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock } endcode +// (10) If post-adder and PREG both present, match for a $mux cell driving +// the 'C' input, where one of the $mux's inputs is the PREG output. +// This indicates an accumulator situation, and one where a $mux exists +// to override the accumulated value: +// +--------------------------------+ +// | ____ | +// +--| \ | +// |$mux|-+ | +// 'C' ---|____/ | | +// | /-------\ +----+ | +// +----+ +-| post- |___|PREG|---+ 'P' +// |MREG|------ | adder | +----+ +// +----+ \-------/ match postAddMux if postAdd if ffP @@ -333,6 +417,11 @@ code sigC sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A); endcode +// (11) If PREG present, match for a greater-than-or-equal $ge cell attached to +// the 'P' output where it is compared to a constant that is a power-of-2: +// e.g. `assign overflow = (PREG >= 2**40);` +// In this scenario, the pattern detector functionality of a DSP48E1 can +// to implement this function match overflow if ffP if param(dsp, \USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET" diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index a31dc80bf..a20d3cdce 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -1,3 +1,25 @@ +// This file describes the second of three pattern matcher setups that +// forms the `xilinx_dsp` pass described in xilinx_dsp.cc +// At a high level, it works as follows: +// (1) Starting from a DSP48E1 cell that (a) doesn't have a CREG already, +// and (b) uses the 'C' port +// (2) Match the driver of the 'C' input to a possible $dff cell (CREG) +// (attached to at most two $mux cells that implement clock-enable or +// reset functionality, using a subpattern discussed below) +// Notes: +// - Separating out CREG packing is necessary since there is no guarantee +// that the cell ordering corresponds to the "expected" case (i.e. the order +// in which they appear in the source) thus the possiblity existed that a +// register got packed as a CREG into a downstream DSP that should have +// otherwise been a PREG of an upstream DSP that had not been visited yet +// - The reason this is separated out from the xilinx_dsp.pmg file is +// for efficiency --- each *.pmg file creates a class of the same basename, +// which when constructed, creates a custom database tailored to the +// pattern(s) contained within. Since the pattern in this file must be +// executed after the pattern contained in xilinx_dsp.pmg, it is necessary +// to reconstruct this database. Separating the two patterns into +// independent files causes two smaller, more specific, databases. + pattern xilinx_dsp_packC udata > unextend @@ -15,13 +37,15 @@ udata dffclock udata dff dffcemux dffrstmux udata dffcepol dffrstpol +// (1) Starting from a DSP48E1 cell that (a) doesn't have a CREG already, +// and (b) uses the 'C' port match dsp select dsp->type.in(\DSP48E1) select param(dsp, \CREG, 1).as_int() == 0 select nusers(port(dsp, \C, SigSpec())) > 1 endmatch -code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC sigP clock +code sigC sigP unextend = [](const SigSpec &sig) { int i; for (i = GetSize(sig)-1; i > 0; i--) @@ -47,7 +71,14 @@ code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC sigP clock } else sigP = P; +endcode +// (2) Match the driver of the 'C' input to a possible $dff cell (CREG) +// (attached to at most two $mux cells that implement clock-enable or +// reset functionality, using a subpattern discussed below) +code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock + // TODO: Any downside to allowing this? + // If this DSP implements an accumulator, do not attempt to match if (sigC == sigP) reject; From 983068103e24c33a1b70eb90dd72fdfaf292e1bd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 12:43:19 -0700 Subject: [PATCH 066/123] Consistency --- passes/pmgen/xilinx_dsp_CREG.pmg | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index a20d3cdce..38a5a8d24 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -45,7 +45,7 @@ match dsp select nusers(port(dsp, \C, SigSpec())) > 1 endmatch -code sigC sigP +code sigC sigP clock unextend = [](const SigSpec &sig) { int i; for (i = GetSize(sig)-1; i > 0; i--) @@ -71,6 +71,8 @@ code sigC sigP } else sigP = P; + + clock = port(dsp, \CLK, SigBit()); endcode // (2) Match the driver of the 'C' input to a possible $dff cell (CREG) @@ -82,8 +84,6 @@ code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock if (sigC == sigP) reject; - clock = port(dsp, \CLK, SigBit()); - argQ = sigC; subpattern(in_dffe); if (dff) { From 7de9c33931020068b285e262bbf239385fcb5c2d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 12:43:56 -0700 Subject: [PATCH 067/123] Fix TODOs --- passes/pmgen/xilinx_dsp.pmg | 15 --------------- passes/pmgen/xilinx_dsp_CREG.pmg | 5 ----- 2 files changed, 20 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index bcf966a8a..6b6151564 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -103,11 +103,6 @@ code sigA sigB sigC sigD sigM clock } else sigM = P; - // TODO: Check if necessary - // This sigM could have no users if downstream $add - // is narrower than $mul result, for example - if (sigM.empty()) - reject; clock = port(dsp, \CLK, SigBit()); endcode @@ -159,16 +154,6 @@ match preAdd optional endmatch -code sigA sigD - // TODO: Check if this is necessary? - if (preAdd) { - sigA = port(preAdd, \A); - sigD = port(preAdd, \B); - if (GetSize(sigA) < GetSize(sigD)) - std::swap(sigA, sigD); - } -endcode - // (4) If pre-adder was present, find match 'A' input for A2REG // If pre-adder was not present, move ADREG to A2REG // Then match 'A' input for A1REG diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 38a5a8d24..5697ee737 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -79,11 +79,6 @@ endcode // (attached to at most two $mux cells that implement clock-enable or // reset functionality, using a subpattern discussed below) code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock - // TODO: Any downside to allowing this? - // If this DSP implements an accumulator, do not attempt to match - if (sigC == sigP) - reject; - argQ = sigC; subpattern(in_dffe); if (dff) { From 6d689726193db4d46f7618ff00707e4f30366ad5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 13:31:44 -0700 Subject: [PATCH 068/123] More comments, cleanup --- passes/pmgen/xilinx_dsp.pmg | 108 ++++++++++++++++++++++--------- passes/pmgen/xilinx_dsp_CREG.pmg | 43 +++++++++--- 2 files changed, 109 insertions(+), 42 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 6b6151564..3523db3a4 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -425,22 +425,42 @@ endcode // ####################### +// Subpattern for matching against input registers, based on knowledge of the +// 'Q' input. +// At a high level: +// (1) Starting from a $dff cell that (partially or fully) drives the given +// 'Q' argument +// (2) Match for a $mux cell implementing synchronous reset semantics --- +// one that exclusively drives the 'D' input of the $dff, with one of its +// $mux inputs being fully zero +// (3) Match for a $mux cell implement clock enable semantics --- one that +// exclusively drives the 'D' input of the $dff (or the other input of +// the reset $mux) and where one of this $mux's inputs is connected to +// the 'Q' output of the $dff subpattern in_dffe arg argD argQ clock code dff = nullptr; - for (auto c : argQ.chunks()) { + for (const auto &c : argQ.chunks()) { + // Abandon matches when 'Q' is a constant if (!c.wire) reject; + // Abandon matches when 'Q' has the keep attribute set if (c.wire->get_bool_attribute(\keep)) reject; - Const init = c.wire->attributes.at(\init, State::Sx); - if (!init.is_fully_undef() && !init.is_fully_zero()) - reject; + // Abandon matches when 'Q' has a non-zero init attribute set + // (not supported by DSP48E1) + Const init = c.wire->attributes.at(\init, Const()); + if (!init.empty()) + for (auto b : init.extract(c.offset, c.width)) + if (b != State::Sx && b != State::S0) + reject; } endcode +// (1) Starting from a $dff cell that (partially or fully) drives the given +// 'Q' argument match ff select ff->type.in($dff) // DSP48E1 does not support clock inversion @@ -453,14 +473,12 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ + filter clock == SigBit() || port(ff, \CLK) == clock + set ffoffset offset endmatch code argQ argD -{ - if (clock != SigBit() && port(ff, \CLK) != clock) - reject; - SigSpec Q = port(ff, \Q); dff = ff; dffclock = port(ff, \CLK); @@ -472,9 +490,11 @@ code argQ argD // has two (ff, ffrstmux) users if (nusers(dffD) > 2) argD = SigSpec(); -} endcode +// (2) Match for a $mux cell implementing synchronous reset semantics --- +// exclusively drives the 'D' input of the $dff, with one of the $mux +// inputs being fully zero match ffrstmux if !argD.empty() select ffrstmux->type.in($mux) @@ -506,6 +526,10 @@ code argD dffrstmux = nullptr; endcode +// (3) Match for a $mux cell implement clock enable semantics --- one that +// exclusively drives the 'D' input of the $dff (or the other input of +// the reset $mux) and where one of this $mux's inputs is connected to +// the 'Q' output of the $dff match ffcemux if !argD.empty() select ffcemux->type.in($mux) @@ -530,16 +554,32 @@ endcode // ####################### +// Subpattern for matching against output registers, based on knowledge of the +// 'D' input. +// At a high level: +// (1) Starting from an optional $mux cell that implements clock enable +// semantics --- one where the given 'D' argument (partially or fully) +// drives one of its two inputs +// (2) Starting from, or continuing onto, another optional $mux cell that +// implements synchronous reset semantics --- one where the given 'D' +// argument (or the clock enable $mux output) drives one of its two inputs +// and where the other input is fully zero +// (3) Match for a $dff cell (whose 'D' input is the 'D' argument, or the +// output of the previous clock enable or reset $mux cells) subpattern out_dffe arg argD argQ clock code dff = nullptr; for (auto c : argD.chunks()) + // Abandon matches when 'D' has the keep attribute set if (c.wire->get_bool_attribute(\keep)) reject; endcode +// (1) Starting from an optional $mux cell that implements clock enable +// semantics --- one where the given 'D' argument (partially or fully) +// drives one of its two inputs match ffcemux select ffcemux->type.in($mux) // ffcemux output must have two users: ffcemux and ff.D @@ -578,6 +618,10 @@ code argD argQ } endcode +// (2) Starting from, or continuing onto, another optional $mux cell that +// implements synchronous reset semantics --- one where the given 'D' +// argument (or the clock enable $mux output) drives one of its two inputs +// and where the other input is fully zero match ffrstmux select ffrstmux->type.in($mux) // ffrstmux output must have two users: ffrstmux and ff.D @@ -616,6 +660,8 @@ code argD argQ } endcode +// (3) Match for a $dff cell (whose 'D' input is the 'D' argument, or the +// output of the previous clock enable or reset $mux cells) match ff select ff->type.in($dff) // DSP48E1 does not support clock inversion @@ -632,32 +678,30 @@ match ff // Check that FF.Q is connected to CE-mux filter !ffcemux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ + filter clock == SigBit() || port(ff, \CLK) == clock + set ffoffset offset endmatch code argQ - if (ff) { - if (clock != SigBit() && port(ff, \CLK) != clock) - reject; - - SigSpec D = port(ff, \D); - SigSpec Q = port(ff, \Q); - if (!ffcemux) { - argQ = argD; - argQ.replace(D, Q); - } - - for (auto c : argQ.chunks()) { - Const init = c.wire->attributes.at(\init, State::Sx); - if (!init.is_fully_undef() && !init.is_fully_zero()) - reject; - } - - dff = ff; - dffQ = argQ; - dffclock = port(ff, \CLK); + SigSpec D = port(ff, \D); + SigSpec Q = port(ff, \Q); + if (!ffcemux) { + argQ = argD; + argQ.replace(D, Q); } - // No enable/reset mux possible without flop - else if (dffcemux || dffrstmux) - reject; + + // Abandon matches when 'Q' has a non-zero init attribute set + // (not supported by DSP48E1) + for (auto c : argQ.chunks()) { + Const init = c.wire->attributes.at(\init, Const()); + if (!init.empty()) + for (auto b : init.extract(c.offset, c.width)) + if (b != State::Sx && b != State::S0) + reject; + } + + dff = ff; + dffQ = argQ; + dffclock = port(ff, \CLK); endcode diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 5697ee737..3d911b478 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -77,7 +77,7 @@ endcode // (2) Match the driver of the 'C' input to a possible $dff cell (CREG) // (attached to at most two $mux cells that implement clock-enable or -// reset functionality, using a subpattern discussed below) +// reset functionality, using the in_dffe subpattern) code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock argQ = sigC; subpattern(in_dffe); @@ -103,22 +103,41 @@ endcode // ####################### +// Subpattern for matching against input registers, based on knowledge of the +// 'Q' input. +// At a high level: +// (1) Starting from a $dff cell that (partially or fully) drives the given +// 'Q' argument +// (2) Match for a $mux cell implementing synchronous reset semantics --- +// one that exclusively drives the 'D' input of the $dff, with one of its +// $mux inputs being fully zero +// (3) Match for a $mux cell implement clock enable semantics --- one that +// exclusively drives the 'D' input of the $dff (or the other input of +// the reset $mux) and where one of this $mux's inputs is connected to +// the 'Q' output of the $dff subpattern in_dffe arg argD argQ clock code dff = nullptr; - for (auto c : argQ.chunks()) { + for (const auto &c : argQ.chunks()) { + // Abandon matches when 'Q' is a constant if (!c.wire) reject; + // Abandon matches when 'Q' has the keep attribute set if (c.wire->get_bool_attribute(\keep)) reject; - Const init = c.wire->attributes.at(\init, State::Sx); - if (!init.is_fully_undef() && !init.is_fully_zero()) - reject; + // Abandon matches when 'Q' has a non-zero init attribute set + // (not supported by DSP48E1) + Const init = c.wire->attributes.at(\init, Const()); + for (auto b : init.extract(c.offset, c.width)) + if (b != State::Sx && b != State::S0) + reject; } endcode +// (1) Starting from a $dff cell that (partially or fully) drives the given +// 'Q' argument match ff select ff->type.in($dff) // DSP48E1 does not support clock inversion @@ -131,14 +150,12 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ + filter clock == SigBit() || port(ff, \CLK) == clock + set ffoffset offset endmatch code argQ argD -{ - if (clock != SigBit() && port(ff, \CLK) != clock) - reject; - SigSpec Q = port(ff, \Q); dff = ff; dffclock = port(ff, \CLK); @@ -150,9 +167,11 @@ code argQ argD // has two (ff, ffrstmux) users if (nusers(dffD) > 2) argD = SigSpec(); -} endcode +// (2) Match for a $mux cell implementing synchronous reset semantics --- +// exclusively drives the 'D' input of the $dff, with one of the $mux +// inputs being fully zero match ffrstmux if !argD.empty() select ffrstmux->type.in($mux) @@ -184,6 +203,10 @@ code argD dffrstmux = nullptr; endcode +// (3) Match for a $mux cell implement clock enable semantics --- one that +// exclusively drives the 'D' input of the $dff (or the other input of +// the reset $mux) and where one of this $mux's inputs is connected to +// the 'Q' output of the $dff match ffcemux if !argD.empty() select ffcemux->type.in($mux) From 52583ecff82eb9dc78e10b7bfd33c1be3d4dcc67 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 13:33:27 -0700 Subject: [PATCH 069/123] Revert "Fix TODOs" This reverts commit 8674a6c68d563908014d16671567459499c6dc99. --- passes/pmgen/xilinx_dsp.pmg | 15 +++++++++++++++ passes/pmgen/xilinx_dsp_CREG.pmg | 5 +++++ 2 files changed, 20 insertions(+) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 3523db3a4..8a2c2caf5 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -103,6 +103,11 @@ code sigA sigB sigC sigD sigM clock } else sigM = P; + // TODO: Check if necessary + // This sigM could have no users if downstream $add + // is narrower than $mul result, for example + if (sigM.empty()) + reject; clock = port(dsp, \CLK, SigBit()); endcode @@ -154,6 +159,16 @@ match preAdd optional endmatch +code sigA sigD + // TODO: Check if this is necessary? + if (preAdd) { + sigA = port(preAdd, \A); + sigD = port(preAdd, \B); + if (GetSize(sigA) < GetSize(sigD)) + std::swap(sigA, sigD); + } +endcode + // (4) If pre-adder was present, find match 'A' input for A2REG // If pre-adder was not present, move ADREG to A2REG // Then match 'A' input for A1REG diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 3d911b478..b87a686a1 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -79,6 +79,11 @@ endcode // (attached to at most two $mux cells that implement clock-enable or // reset functionality, using the in_dffe subpattern) code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock + // TODO: Any downside to allowing this? + // If this DSP implements an accumulator, do not attempt to match + if (sigC == sigP) + reject; + argQ = sigC; subpattern(in_dffe); if (dff) { From 77d7a5c14a6cf7c16b69338ed91d1b9166dba065 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 13:38:09 -0700 Subject: [PATCH 070/123] Retry on fixing TODOs --- passes/pmgen/xilinx_dsp.pmg | 9 +-------- passes/pmgen/xilinx_dsp_CREG.pmg | 5 ----- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 8a2c2caf5..dbc3f7455 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -100,14 +100,10 @@ code sigA sigB sigC sigD sigM clock sigM.append(P[i]); } log_assert(nusers(P.extract_end(i)) <= 1); + log_assert(!sigM.empty()); } else sigM = P; - // TODO: Check if necessary - // This sigM could have no users if downstream $add - // is narrower than $mul result, for example - if (sigM.empty()) - reject; clock = port(dsp, \CLK, SigBit()); endcode @@ -160,12 +156,9 @@ match preAdd endmatch code sigA sigD - // TODO: Check if this is necessary? if (preAdd) { sigA = port(preAdd, \A); sigD = port(preAdd, \B); - if (GetSize(sigA) < GetSize(sigD)) - std::swap(sigA, sigD); } endcode diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index b87a686a1..3d911b478 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -79,11 +79,6 @@ endcode // (attached to at most two $mux cells that implement clock-enable or // reset functionality, using the in_dffe subpattern) code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock - // TODO: Any downside to allowing this? - // If this DSP implements an accumulator, do not attempt to match - if (sigC == sigP) - reject; - argQ = sigC; subpattern(in_dffe); if (dff) { From 8027ebf05b7538e501b4903cab9c2ce6a23610ff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 21:42:46 -0700 Subject: [PATCH 071/123] Restore optimisation for sigM.empty() --- passes/pmgen/xilinx_dsp.pmg | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index dbc3f7455..77d4850d4 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -100,7 +100,10 @@ code sigA sigB sigC sigD sigM clock sigM.append(P[i]); } log_assert(nusers(P.extract_end(i)) <= 1); - log_assert(!sigM.empty()); + // This sigM could have no users if downstream sinks (e.g. $add) is + // narrower than $mul result, for example + if (sigM.empty()) + reject; } else sigM = P; From 14e4aeece6adc0808ab1876f01752acb0833185a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 21:45:31 -0700 Subject: [PATCH 072/123] Fix comment --- passes/pmgen/xilinx_dsp.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 489887207..886e01c0f 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -614,7 +614,7 @@ struct XilinxDspPass : public Pass { xilinx_simd_pack(module, module->selected_cells()); // Match for all features ([ABDMP][12]?REG, pre-adder, - // (post-adder, pattern detector, etc.) except for CREG + // post-adder, pattern detector, etc.) except for CREG { xilinx_dsp_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_pack(xilinx_dsp_pack); From 12fd2ec4f05ce5efda2a2d2e4d37aef013f2baf9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 22:24:15 -0700 Subject: [PATCH 073/123] Improve comments for xilinx_dsp_CREG --- passes/pmgen/xilinx_dsp_CREG.pmg | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 3d911b478..3f8486406 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -7,11 +7,12 @@ // (attached to at most two $mux cells that implement clock-enable or // reset functionality, using a subpattern discussed below) // Notes: -// - Separating out CREG packing is necessary since there is no guarantee -// that the cell ordering corresponds to the "expected" case (i.e. the order -// in which they appear in the source) thus the possiblity existed that a -// register got packed as a CREG into a downstream DSP that should have -// otherwise been a PREG of an upstream DSP that had not been visited yet +// - Running CREG packing after xilinx_dsp_pack is necessary since there is no +// guarantee that the cell ordering corresponds to the "expected" case (i.e. +// the order in which they appear in the source) thus the possiblity existed +// that a register got packed as a CREG into a downstream DSP that should +// have otherwise been a PREG of an upstream DSP that had not been visited +// yet // - The reason this is separated out from the xilinx_dsp.pmg file is // for efficiency --- each *.pmg file creates a class of the same basename, // which when constructed, creates a custom database tailored to the @@ -28,7 +29,7 @@ state sigC sigP state ffCcepol ffCrstpol state ffC ffCcemux ffCrstmux -// subpattern +// Variables used for subpatterns state argQ argD state ffcepol ffrstpol state ffoffset From 792cd31052d32d661a995df0c46f5cb9f27b566b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 22:25:30 -0700 Subject: [PATCH 074/123] Add comments for xilinx_dsp_cascade --- passes/pmgen/xilinx_dsp_cascade.pmg | 112 +++++++++++++++++++++++++--- 1 file changed, 100 insertions(+), 12 deletions(-) diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 6f4ac5849..42d1aee6c 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -1,3 +1,46 @@ +// This file describes the third of three pattern matcher setups that +// forms the `xilinx_dsp` pass described in xilinx_dsp.cc +// At a high level, it works as follows: +// (1) Starting from a DSP48E1 cell that (a) has the Z multiplexer +// (controlled by OPMODE[6:4]) set to zero and (b) doesn't already +// use the 'PCOUT' port +// (2.1) Match another DSP48E1 cell that (a) does not have the CREG enabled, +// (b) has its Z multiplexer output set to the 'C' port, which is +// driven by the 'P' output of the previous DSP cell, and (c) has its +// 'PCIN' port unused +// (2.2) Same as (2.1) but with the 'C' port driven by the 'P' output of the +// previous DSP cell right-shifted by 17 bits +// (3) For this subequent DSP48E1 match (i.e. PCOUT -> PCIN cascade exists) +// if (a) the previous DSP48E1 uses either the A2REG or A1REG, (b) this +// DSP48 does not use A2REG nor A1REG, (c) this DSP48E1 does not already +// have an ACOUT -> ACIN cascade, (d) the previous DSP does not already +// use its ACOUT port, then examine if an ACOUT -> ACIN cascade +// opportunity exists by matching for a $dff-with-optional-clock-enable- +// or-reset and checking that the 'D' input of this register is the same +// as the 'A' input of the previous DSP +// (4) Same as (3) but for BCOUT -> BCIN cascade +// (5) Recursively go to (2.1) until no more matches possible, keeping track +// of the longest possible chain found +// (6) The longest chain is then divided into chunks of no more than +// MAX_DSP_CASCADE in length (to prevent long cascades that exceed the +// height of a DSP column) with each DSP in each chunk being rewritten +// to use [ABP]COUT -> [ABP]CIN cascading as appropriate +// Notes: +// - Currently, [AB]COUT -> [AB]COUT cascades (3 or 4) are only considered +// if a PCOUT -> PCIN cascade is (2.1 or 2.2) first identified; this need +// not be the case --- [AB] cascades can exist independently of a P cascade +// (though all three cascades must come from the same DSP). This situation +// is not handled currently. +// - In addition, [AB]COUT -> [AB]COUT cascades (3 or 4) are currently +// conservative in that they examine the situation where (a) the previous +// DSP has [AB]2REG or [AB]1REG enabled, (b) that the downstream DSP has no +// registers enabled, and (c) that there exists only one additional register +// between the upstream and downstream DSPs. This can certainly be relaxed +// to identify situations ranging from (i) neither DSP uses any registers, +// to (ii) upstream DSP has 2 registers, downstream DSP has 2 registers, and +// there exists a further 2 registers between them. This remains a TODO +// item. + pattern xilinx_dsp_cascade udata > unextend @@ -6,7 +49,7 @@ state next state clock state AREG BREG -// subpattern +// Variables used for subpatterns state argQ argD state ffcepol ffrstpol state ffoffset @@ -19,12 +62,19 @@ code #define MAX_DSP_CASCADE 20 endcode +// (1) Starting from a DSP48E1 cell that (a) has the Z multiplexer +// (controlled by OPMODE[6:4]) set to zero and (b) doesn't already +// use the 'PCOUT' port match first select first->type.in(\DSP48E1) select port(first, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("000") select nusers(port(first, \PCOUT, SigSpec())) <= 1 endmatch +// (6) The longest chain is then divided into chunks of no more than +// MAX_DSP_CASCADE in length (to prevent long cascades that exceed the +// height of a DSP column) with each DSP in each chunk being rewritten +// to use [ABP]COUT -> [ABP]CIN cascading as appropriate code longest_chain.clear(); chain.emplace_back(first, -1, -1, -1); @@ -106,6 +156,10 @@ subpattern tail arg first arg next +// (2.1) Match another DSP48E1 cell that (a) does not have the CREG enabled, +// (b) has its Z multiplexer output set to the 'C' port, which is +// driven by the 'P' output of the previous DSP cell, and (c) has its +// 'PCIN' port unused match nextP select nextP->type.in(\DSP48E1) select !param(nextP, \CREG, State::S1).as_bool() @@ -116,6 +170,8 @@ match nextP semioptional endmatch +// (2.2) Same as (2.1) but with the 'C' port driven by the 'P' output of the +// previous DSP cell right-shifted by 17 bits match nextP_shift17 if !nextP select nextP_shift17->type.in(\DSP48E1) @@ -145,6 +201,14 @@ code next } endcode +// (3) For this subequent DSP48E1 match (i.e. PCOUT -> PCIN cascade exists) +// if (a) the previous DSP48E1 uses either the A2REG or A1REG, (b) this +// DSP48 does not use A2REG nor A1REG, (c) this DSP48E1 does not already +// have an ACOUT -> ACIN cascade, (d) the previous DSP does not already +// use its ACOUT port, then examine if an ACOUT -> ACIN cascade +// opportunity exists by matching for a $dff-with-optional-clock-enable- +// or-reset and checking that the 'D' input of this register is the same +// as the 'A' input of the previous DSP code argQ clock AREG AREG = -1; if (next) { @@ -152,7 +216,6 @@ code argQ clock AREG if (param(prev, \AREG, 2).as_int() > 0 && param(next, \AREG, 2).as_int() > 0 && param(next, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && - port(next, \ACIN, SigSpec()).is_fully_zero() && nusers(port(prev, \ACOUT, SigSpec())) <= 1) { argQ = unextend(port(next, \A)); clock = port(prev, \CLK); @@ -174,6 +237,7 @@ reject_AREG: ; } endcode +// (4) Same as (3) but for BCOUT -> BCIN cascade code argQ clock BREG BREG = -1; if (next) { @@ -203,13 +267,14 @@ reject_BREG: ; } endcode +// (5) Recursively go to (2.1) until no more matches possible, recording the +// longest possible chain code if (next) { chain.emplace_back(next, nextP_shift17 ? 17 : nextP ? 0 : -1, AREG, BREG); SigSpec sigC = unextend(port(next, \C)); - // TODO: Cannot use 'reject' since semioptional if (nextP_shift17) { if (GetSize(sigC)+17 <= GetSize(port(std::get<0>(chain.back()), \P)) && port(std::get<0>(chain.back()), \P).extract(17, GetSize(sigC)) != sigC) @@ -232,22 +297,41 @@ endcode // ####################### +// Subpattern for matching against input registers, based on knowledge of the +// 'Q' input. +// At a high level: +// (1) Starting from a $dff cell that (partially or fully) drives the given +// 'Q' argument +// (2) Match for a $mux cell implementing synchronous reset semantics --- +// one that exclusively drives the 'D' input of the $dff, with one of its +// $mux inputs being fully zero +// (3) Match for a $mux cell implement clock enable semantics --- one that +// exclusively drives the 'D' input of the $dff (or the other input of +// the reset $mux) and where one of this $mux's inputs is connected to +// the 'Q' output of the $dff subpattern in_dffe arg argD argQ clock code dff = nullptr; - for (auto c : argQ.chunks()) { + for (const auto &c : argQ.chunks()) { + // Abandon matches when 'Q' is a constant if (!c.wire) reject; + // Abandon matches when 'Q' has the keep attribute set if (c.wire->get_bool_attribute(\keep)) reject; - Const init = c.wire->attributes.at(\init, State::Sx); - if (!init.is_fully_undef() && !init.is_fully_zero()) - reject; + // Abandon matches when 'Q' has a non-zero init attribute set + // (not supported by DSP48E1) + Const init = c.wire->attributes.at(\init, Const()); + for (auto b : init.extract(c.offset, c.width)) + if (b != State::Sx && b != State::S0) + reject; } endcode +// (1) Starting from a $dff cell that (partially or fully) drives the given +// 'Q' argument match ff select ff->type.in($dff) // DSP48E1 does not support clock inversion @@ -260,14 +344,12 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ + filter clock == SigBit() || port(ff, \CLK) == clock + set ffoffset offset endmatch code argQ argD -{ - if (clock != SigBit() && port(ff, \CLK) != clock) - reject; - SigSpec Q = port(ff, \Q); dff = ff; dffclock = port(ff, \CLK); @@ -279,9 +361,11 @@ code argQ argD // has two (ff, ffrstmux) users if (nusers(dffD) > 2) argD = SigSpec(); -} endcode +// (2) Match for a $mux cell implementing synchronous reset semantics --- +// exclusively drives the 'D' input of the $dff, with one of the $mux +// inputs being fully zero match ffrstmux if !argD.empty() select ffrstmux->type.in($mux) @@ -313,6 +397,10 @@ code argD dffrstmux = nullptr; endcode +// (3) Match for a $mux cell implement clock enable semantics --- one that +// exclusively drives the 'D' input of the $dff (or the other input of +// the reset $mux) and where one of this $mux's inputs is connected to +// the 'Q' output of the $dff match ffcemux if !argD.empty() select ffcemux->type.in($mux) From 6c5e1234e19159b7577a5e64a7a463142160f7ff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 22:30:14 -0700 Subject: [PATCH 075/123] Add comment on why partial multipliers are 18x18 --- techlibs/xilinx/synth_xilinx.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 41429b338..4fe287744 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -342,10 +342,14 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_dsp", "(skip if '-nodsp')")) { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " - "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers - "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller - "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 " + "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally + // limited to 18x18 in order to take + // advantage of the (PCOUT << 17) -> PCIN + // dedicated cascade chain capability + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); run("select a:mul2dsp"); run("setattr -unset mul2dsp"); run("opt_expr -fine"); From ebb059896a55efacf1d90f78dbd25faff30969e2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 5 Oct 2019 08:53:01 -0700 Subject: [PATCH 076/123] Add note on pattern detector --- passes/pmgen/xilinx_dsp.pmg | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 77d4850d4..09d94ff4b 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -44,9 +44,13 @@ // DSP48E1 cells inferred from multiply operations by Yosys, as well as for // user instantiations that may already contain the cells being packed... // (though the latter is currently untested) -// - Since the $dff-with-clock-enable-or-reset-mux pattern is used for each -// *REG match, it has been factored out into two subpatterns: in_dffe -// out_dffe located at the bottom of this file +// - Since the $dff-with-optional-clock-enable-or-reset-mux pattern is used +// for each *REG match, it has been factored out into two subpatterns: +// in_dffe and out_dffe located at the bottom of this file. +// - Matching for pattern detector features is currently incomplete. For +// example, matching for underflow as well as overflow detection is +// possible, as would auto-reset, enabling saturated arithmetic, detecting +// custom patterns, etc. pattern xilinx_dsp_pack From 991c2ca95bfac2bedd9fd622dbef15611021a8be Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 5 Oct 2019 08:56:37 -0700 Subject: [PATCH 077/123] Add comment on why we have to match for clock-enable/reset muxes --- passes/pmgen/xilinx_dsp.pmg | 5 ++++- passes/pmgen/xilinx_dsp_CREG.pmg | 4 +++- passes/pmgen/xilinx_dsp_cascade.pmg | 5 ++++- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 09d94ff4b..604aa222b 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -441,7 +441,10 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. +// 'Q' input. Typically, identifying registers with clock-enable and reset +// capability would be a task would be handled by other Yosys passes such as +// dff2dffe, but since DSP inference happens much before this, these patterns +// have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 3f8486406..2408d483a 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -105,7 +105,9 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. +// 'Q' input. Typically, this task would be handled by other Yosys passes +// such as dff2dffe, but since DSP inference happens much before this, these +// patterns have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 42d1aee6c..7a32df2b7 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -298,7 +298,10 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. +// 'Q' input. Typically, identifying registers with clock-enable and reset +// capability would be a task would be handled by other Yosys passes such as +// dff2dffe, but since DSP inference happens much before this, these patterns +// have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument From f90a4b1e24e36943a343bd36315b6029dd6cd044 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 5 Oct 2019 08:57:37 -0700 Subject: [PATCH 078/123] Missed this --- passes/pmgen/xilinx_dsp_CREG.pmg | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 2408d483a..a57043009 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -105,9 +105,10 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. Typically, this task would be handled by other Yosys passes -// such as dff2dffe, but since DSP inference happens much before this, these -// patterns have to be manually identified. +// 'Q' input. Typically, identifying registers with clock-enable and reset +// capability would be a task would be handled by other Yosys passes such as +// dff2dffe, but since DSP inference happens much before this, these patterns +// have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument From 10d0bad67e91c45813a1185753fa4dcbcc2c86d8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 5 Oct 2019 18:13:04 +0200 Subject: [PATCH 079/123] Update README.md --- passes/pmgen/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 2f5b8d0b2..39560839f 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -190,7 +190,7 @@ create matches for different sections of a cell. For example: select pmux->type == $pmux slice idx GetSize(port(pmux, \S)) index port(pmux, \S)[idx] === port(eq, \Y) - set pmux_slice idx + set pmux_slice idx endmatch The first argument to `slice` is the local variable name used to identify the From 5c68da4150f8e5367138f2c7187f707b20cc19db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 5 Oct 2019 09:27:12 -0700 Subject: [PATCH 080/123] Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf --- passes/pmgen/ice40_wrapcarry.pmg | 4 ++++ tests/ice40/wrapcarry.ys | 22 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 tests/ice40/wrapcarry.ys diff --git a/passes/pmgen/ice40_wrapcarry.pmg b/passes/pmgen/ice40_wrapcarry.pmg index 9e64c7467..bb59edb0c 100644 --- a/passes/pmgen/ice40_wrapcarry.pmg +++ b/passes/pmgen/ice40_wrapcarry.pmg @@ -9,3 +9,7 @@ match lut index port(lut, \I1) === port(carry, \I0) index port(lut, \I2) === port(carry, \I1) endmatch + +code + accept; +endcode diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys new file mode 100644 index 000000000..10c029e68 --- /dev/null +++ b/tests/ice40/wrapcarry.ys @@ -0,0 +1,22 @@ +read_verilog < Date: Tue, 8 Oct 2019 12:41:24 -0700 Subject: [PATCH 081/123] Revert "Be mindful that sigmap(wire) could have dupes when checking \init" This reverts commit f46ac1df9f8847dac9d9851f2f948d93a1064ff1. --- passes/sat/sat.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 93a4f225e..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -265,18 +265,15 @@ struct SatHelper RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); log_assert(lhs.size() == rhs.size()); - dict seen_init; RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); i--; } - else - seen_init[bit] = rhs[i]; } if (removed_bits.size()) From 3fb604c75d3e8ee45d35fac8b787cb95a8adcf84 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 8 Oct 2019 12:41:26 -0700 Subject: [PATCH 082/123] Revert "Add test that is expecting to fail" This reverts commit c28d4b804720c2cf0086e921748219150e9631b5. --- tests/sat/initval.ys | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 1627a37e3..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,23 +2,3 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts - -read_verilog < Date: Thu, 10 Oct 2019 11:31:33 +0200 Subject: [PATCH 083/123] xilinx: Add simulation model for IBUFG. --- techlibs/xilinx/cells_sim.v | 11 +++++++++++ techlibs/xilinx/cells_xtra.py | 6 +++--- techlibs/xilinx/xc6s_cells_xtra.v | 10 ---------- techlibs/xilinx/xc6v_cells_xtra.v | 10 ---------- techlibs/xilinx/xc7_cells_xtra.v | 10 ---------- 5 files changed, 14 insertions(+), 33 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 28cd208cd..03985b1be 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -38,6 +38,17 @@ module IBUF( assign O = I; endmodule +module IBUFG( + output O, + (* iopad_external_pin *) + input I); + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + assign O = I; +endmodule + module OBUF( (* iopad_external_pin *) output O, diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index ee20ae992..9a4747ff3 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -53,7 +53,7 @@ XC6S_CELLS = [ # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), @@ -174,7 +174,7 @@ XC6V_CELLS = [ Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), @@ -307,7 +307,7 @@ XC7_CELLS = [ Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), diff --git a/techlibs/xilinx/xc6s_cells_xtra.v b/techlibs/xilinx/xc6s_cells_xtra.v index f8dcce81d..7c0462b52 100644 --- a/techlibs/xilinx/xc6s_cells_xtra.v +++ b/techlibs/xilinx/xc6s_cells_xtra.v @@ -1282,16 +1282,6 @@ module IBUFDS_DIFF_OUT (...); input IB; endmodule -module IBUFG (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; -endmodule - module IBUFGDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v index d9e06eae2..87656fa49 100644 --- a/techlibs/xilinx/xc6v_cells_xtra.v +++ b/techlibs/xilinx/xc6v_cells_xtra.v @@ -1821,16 +1821,6 @@ module IBUFDS_GTHE1 (...); input IB; endmodule -module IBUFG (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; -endmodule - module IBUFGDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v index f36e4baa2..10eea4a5f 100644 --- a/techlibs/xilinx/xc7_cells_xtra.v +++ b/techlibs/xilinx/xc7_cells_xtra.v @@ -3932,16 +3932,6 @@ module IBUFDS_INTERMDISABLE (...); input INTERMDISABLE; endmodule -module IBUFG (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; -endmodule - module IBUFGDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; From 3b44e80d4babb57f4b7c5325f666f0731a4d878b Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 10 Oct 2019 15:55:16 +0100 Subject: [PATCH 084/123] ecp5: Set syn_useioff on IO FFs to enable packing Signed-off-by: David Shah --- techlibs/ecp5/cells_ff.vh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh index 0c9689ebd..501c1b3b2 100644 --- a/techlibs/ecp5/cells_ff.vh +++ b/techlibs/ecp5/cells_ff.vh @@ -23,15 +23,15 @@ module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLI // module FL1S3AY(); endmodule // Diamond I/O registers -module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule // TODO: Diamond I/O latches // module IFS1S1B(input PD, D, SCLK, output Q); endmodule From 7b1a6706d801773ec44d00bda0fd292c50fe39b7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 10 Oct 2019 15:58:31 +0100 Subject: [PATCH 085/123] ecp5: Add attrmvcp to copy syn_useioff to driving FF Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 80aa1dbc5..a79dee31f 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -297,6 +297,7 @@ struct SynthEcp5Pass : public ScriptPass run("simplemap"); run("ecp5_ffinit"); run("ecp5_gsr"); + run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); } From e1d4e683b42bb1b75acb4054a94610cdc9fec0e7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 11 Oct 2019 14:50:33 +0100 Subject: [PATCH 086/123] ecp5: Add ECLKBRIDGECS blackbox Signed-off-by: David Shah --- techlibs/ecp5/cells_bb.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 0a5046db2..ae124e7a3 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -333,6 +333,13 @@ module ECLKSYNCB( ); endmodule +(* blackbox *) +module ECLKBRIDGECS( + input CLK0, CLK1, SEL, + output ECSOUT +); +endmodule + (* blackbox *) module DCCA( input CLKI, CE, From 935d3e19e2ddc315d06b4a7fe649f06578eeeb81 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 00:00:27 +0200 Subject: [PATCH 087/123] Add .blackbox support to blif front-end Signed-off-by: Clifford Wolf --- frontends/blif/blifparse.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index d17cacf29..bfcfad78a 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -174,6 +174,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (module == nullptr) goto error; + if (!strcmp(cmd, ".blackbox")) + { + module->attributes["\\blackbox"] = RTLIL::Const(1); + continue; + } + if (!strcmp(cmd, ".end")) { for (auto &wp : wideports_cache) From 71936209cf194c06dc59d5e17bf3c153a000892f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 09:06:57 +0200 Subject: [PATCH 088/123] Fix parsing of .cname BLIF statements Signed-off-by: Clifford Wolf --- frontends/blif/blifparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index bfcfad78a..cab210605 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -286,7 +286,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto error_with_reason; } - module->rename(lastcell, p); + module->rename(lastcell, RTLIL::escape_id(p)); continue; } From af61d924419844b90bf6d54453489b3e41b7e353 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 10:43:47 +0200 Subject: [PATCH 089/123] Disable left-over log_debug in peepopt_dffmux.pmg Signed-off-by: Clifford Wolf --- passes/pmgen/peepopt_dffmux.pmg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index bfd155c58..15c8dc22f 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -76,7 +76,7 @@ code int i = width-1; while (i > 1) { - log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]); + // log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]); if (D[i] != D[i-1]) break; if (!cmpx(rst[i], rst[i-1])) From bb0851bfc52455f2d93ee878f1876a691564b4ed Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 11:40:01 +0200 Subject: [PATCH 090/123] Move GENERATE_PATTERN macro to separate utility header Signed-off-by: Clifford Wolf --- passes/pmgen/generate.h | 140 +++++++++++++++++++++++++++++++++++++ passes/pmgen/pmgen.py | 16 ++++- passes/pmgen/test_pmgen.cc | 129 +--------------------------------- 3 files changed, 157 insertions(+), 128 deletions(-) create mode 100644 passes/pmgen/generate.h diff --git a/passes/pmgen/generate.h b/passes/pmgen/generate.h new file mode 100644 index 000000000..354583de5 --- /dev/null +++ b/passes/pmgen/generate.h @@ -0,0 +1,140 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef PMGEN_GENERATE +#define PMGEN_GENERATE + +#define GENERATE_PATTERN(pmclass, pattern) \ + generate_pattern([](pmclass &pm, std::function f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design) + +void pmtest_addports(Module *module) +{ + pool driven_bits, used_bits; + SigMap sigmap(module); + int icnt = 0, ocnt = 0; + + for (auto cell : module->cells()) + for (auto conn : cell->connections()) + { + if (cell->input(conn.first)) + for (auto bit : sigmap(conn.second)) + used_bits.insert(bit); + if (cell->output(conn.first)) + for (auto bit : sigmap(conn.second)) + driven_bits.insert(bit); + } + + for (auto wire : vector(module->wires())) + { + SigSpec ibits, obits; + for (auto bit : sigmap(wire)) { + if (!used_bits.count(bit)) + obits.append(bit); + if (!driven_bits.count(bit)) + ibits.append(bit); + } + if (!ibits.empty()) { + Wire *w = module->addWire(stringf("\\i%d", icnt++), GetSize(ibits)); + w->port_input = true; + module->connect(ibits, w); + } + if (!obits.empty()) { + Wire *w = module->addWire(stringf("\\o%d", ocnt++), GetSize(obits)); + w->port_output = true; + module->connect(w, obits); + } + } + + module->fixup_ports(); +} + +template +void generate_pattern(std::function)> run, const char *pmclass, const char *pattern, Design *design) +{ + log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass); + + int modcnt = 0; + int maxmodcnt = 100; + int maxsubcnt = 4; + int timeout = 0; + vector mods; + + while (modcnt < maxmodcnt) + { + int submodcnt = 0, itercnt = 0, cellcnt = 0; + Module *mod = design->addModule(NEW_ID); + + while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000) + { + if (timeout++ > 10000) + log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n"); + + pm matcher(mod, mod->cells()); + + matcher.rng(1); + matcher.rngseed += modcnt; + matcher.rng(1); + matcher.rngseed += submodcnt; + matcher.rng(1); + matcher.rngseed += itercnt; + matcher.rng(1); + matcher.rngseed += cellcnt; + matcher.rng(1); + + if (GetSize(mod->cells()) != cellcnt) + { + bool found_match = false; + run(matcher, [&](){ found_match = true; }); + cellcnt = GetSize(mod->cells()); + + if (found_match) { + Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d", + pmclass, pattern, modcnt++)); + log("Creating module %s with %d cells.\n", log_id(m), cellcnt); + mod->cloneInto(m); + pmtest_addports(m); + mods.push_back(m); + submodcnt++; + timeout = 0; + } + } + + matcher.generate_mode = true; + run(matcher, [](){}); + } + + if (submodcnt && maxsubcnt < (1 << 16)) + maxsubcnt *= 2; + + design->remove(mod); + } + + Module *m = design->addModule(stringf("\\pmtest_%s_%s", pmclass, pattern)); + log("Creating module %s with %d cells.\n", log_id(m), GetSize(mods)); + for (auto mod : mods) { + Cell *c = m->addCell(mod->name, mod->name); + for (auto port : mod->ports) { + Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port))); + c->setPort(port, w); + } + } + pmtest_addports(m); +} + +#endif diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 39a09991d..df0ffaff2 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -362,6 +362,7 @@ with open(outfile, "w") as f: print(" Module *module;", file=f) print(" SigMap sigmap;", file=f) print(" std::function on_accept;", file=f) + print(" bool setup_done;", file=f) print(" bool generate_mode;", file=f) print(" int accept_cnt;", file=f) print("", file=f) @@ -477,7 +478,17 @@ with open(outfile, "w") as f: print("", file=f) print(" {}_pm(Module *module, const vector &cells) :".format(prefix), file=f) - print(" module(module), sigmap(module), generate_mode(false), rngseed(12345678) {", file=f) + print(" module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f) + print(" setup(cells);", file=f) + print(" }", file=f) + print("", file=f) + + print(" {}_pm(Module *module) :".format(prefix), file=f) + print(" module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f) + print(" }", file=f) + print("", file=f) + + print(" void setup(const vector &cells) {", file=f) for current_pattern in sorted(patterns.keys()): for s, t in sorted(udata_types[current_pattern].items()): if t.endswith("*"): @@ -485,6 +496,8 @@ with open(outfile, "w") as f: else: print(" ud_{}.{} = {}();".format(current_pattern, s, t), file=f) current_pattern = None + print(" log_assert(!setup_done);", file=f) + print(" setup_done = true;", file=f) print(" for (auto port : module->ports)", file=f) print(" add_siguser(module->wire(port), nullptr);", file=f) print(" for (auto cell : module->cells())", file=f) @@ -539,6 +552,7 @@ with open(outfile, "w") as f: for current_pattern in sorted(patterns.keys()): print(" int run_{}(std::function on_accept_f) {{".format(current_pattern), file=f) + print(" log_assert(setup_done);", file=f) print(" accept_cnt = 0;", file=f) print(" on_accept = on_accept_f;", file=f) print(" rollback = 0;", file=f) diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 4f3eec935..72dc18dcc 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -23,13 +23,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -// for peepopt_pm -bool did_something; - #include "passes/pmgen/test_pmgen_pm.h" #include "passes/pmgen/ice40_dsp_pm.h" #include "passes/pmgen/xilinx_srl_pm.h" -#include "passes/pmgen/peepopt_pm.h" + +#include "generate.h" void reduce_chain(test_pmgen_pm &pm) { @@ -118,123 +116,6 @@ void opt_eqpmux(test_pmgen_pm &pm) log(" -> %s (%s)\n", log_id(c), log_id(c->type)); } -#define GENERATE_PATTERN(pmclass, pattern) \ - generate_pattern([](pmclass &pm, std::function f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design) - -void pmtest_addports(Module *module) -{ - pool driven_bits, used_bits; - SigMap sigmap(module); - int icnt = 0, ocnt = 0; - - for (auto cell : module->cells()) - for (auto conn : cell->connections()) - { - if (cell->input(conn.first)) - for (auto bit : sigmap(conn.second)) - used_bits.insert(bit); - if (cell->output(conn.first)) - for (auto bit : sigmap(conn.second)) - driven_bits.insert(bit); - } - - for (auto wire : vector(module->wires())) - { - SigSpec ibits, obits; - for (auto bit : sigmap(wire)) { - if (!used_bits.count(bit)) - obits.append(bit); - if (!driven_bits.count(bit)) - ibits.append(bit); - } - if (!ibits.empty()) { - Wire *w = module->addWire(stringf("\\i%d", icnt++), GetSize(ibits)); - w->port_input = true; - module->connect(ibits, w); - } - if (!obits.empty()) { - Wire *w = module->addWire(stringf("\\o%d", ocnt++), GetSize(obits)); - w->port_output = true; - module->connect(w, obits); - } - } - - module->fixup_ports(); -} - -template -void generate_pattern(std::function)> run, const char *pmclass, const char *pattern, Design *design) -{ - log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass); - - int modcnt = 0; - int maxmodcnt = 100; - int maxsubcnt = 4; - int timeout = 0; - vector mods; - - while (modcnt < maxmodcnt) - { - int submodcnt = 0, itercnt = 0, cellcnt = 0; - Module *mod = design->addModule(NEW_ID); - - while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000) - { - if (timeout++ > 10000) - log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n"); - - pm matcher(mod, mod->cells()); - - matcher.rng(1); - matcher.rngseed += modcnt; - matcher.rng(1); - matcher.rngseed += submodcnt; - matcher.rng(1); - matcher.rngseed += itercnt; - matcher.rng(1); - matcher.rngseed += cellcnt; - matcher.rng(1); - - if (GetSize(mod->cells()) != cellcnt) - { - bool found_match = false; - run(matcher, [&](){ found_match = true; }); - cellcnt = GetSize(mod->cells()); - - if (found_match) { - Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d", - pmclass, pattern, modcnt++)); - log("Creating module %s with %d cells.\n", log_id(m), cellcnt); - mod->cloneInto(m); - pmtest_addports(m); - mods.push_back(m); - submodcnt++; - timeout = 0; - } - } - - matcher.generate_mode = true; - run(matcher, [](){}); - } - - if (submodcnt && maxsubcnt < (1 << 16)) - maxsubcnt *= 2; - - design->remove(mod); - } - - Module *m = design->addModule(stringf("\\pmtest_%s_%s", pmclass, pattern)); - log("Creating module %s with %d cells.\n", log_id(m), GetSize(mods)); - for (auto mod : mods) { - Cell *c = m->addCell(mod->name, mod->name); - for (auto port : mod->ports) { - Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port))); - c->setPort(port, w); - } - } - pmtest_addports(m); -} - struct TestPmgenPass : public Pass { TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { } void help() YS_OVERRIDE @@ -355,12 +236,6 @@ struct TestPmgenPass : public Pass { if (pattern == "xilinx_srl.variable") return GENERATE_PATTERN(xilinx_srl_pm, variable); - if (pattern == "peepopt-muldiv") - return GENERATE_PATTERN(peepopt_pm, muldiv); - - if (pattern == "peepopt-shiftmul") - return GENERATE_PATTERN(peepopt_pm, shiftmul); - log_cmd_error("Unknown pattern: %s\n", pattern.c_str()); } From b8774ae849cb6aa54a852a245f8634afaac1eb76 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 11:40:32 +0200 Subject: [PATCH 091/123] Fix dffmux peepopt init handling Signed-off-by: Clifford Wolf --- passes/pmgen/peepopt.cc | 76 ++++++++++++++++++++++++++++++--- passes/pmgen/peepopt_dffmux.pmg | 64 ++++++++++++++++++--------- 2 files changed, 113 insertions(+), 27 deletions(-) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index 72b02127a..2230145df 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -24,8 +24,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something; +dict initbits; +pool rminitbits; #include "passes/pmgen/peepopt_pm.h" +#include "generate.h" struct PeepoptPass : public Pass { PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { } @@ -40,27 +43,86 @@ struct PeepoptPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + std::string genmode; + log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-singleton") { - // singleton_mode = true; - // continue; - // } + if (args[argidx] == "-generate" && argidx+1 < args.size()) { + genmode = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); - for (auto module : design->selected_modules()) { + if (!genmode.empty()) + { + initbits.clear(); + rminitbits.clear(); + + if (genmode == "shiftmul") + GENERATE_PATTERN(peepopt_pm, shiftmul); + else if (genmode == "muldiv") + GENERATE_PATTERN(peepopt_pm, muldiv); + else if (genmode == "dffmux") + GENERATE_PATTERN(peepopt_pm, dffmux); + else + log_abort(); + return; + } + + for (auto module : design->selected_modules()) + { did_something = true; - while (did_something) { + + while (did_something) + { did_something = false; - peepopt_pm pm(module, module->selected_cells()); + initbits.clear(); + rminitbits.clear(); + + peepopt_pm pm(module); + + for (auto w : module->wires()) { + auto it = w->attributes.find(ID(init)); + if (it != w->attributes.end()) { + SigSpec sig = pm.sigmap(w); + Const val = it->second; + int len = std::min(GetSize(sig), GetSize(val)); + for (int i = 0; i < len; i++) { + if (sig[i].wire == nullptr) + continue; + if (val[i] != State::S0 && val[i] != State::S1) + continue; + initbits[sig[i]] = val[i]; + } + } + } + + pm.setup(module->selected_cells()); + pm.run_shiftmul(); pm.run_muldiv(); pm.run_dffmux(); + + for (auto w : module->wires()) { + auto it = w->attributes.find(ID(init)); + if (it != w->attributes.end()) { + SigSpec sig = pm.sigmap(w); + Const &val = it->second; + int len = std::min(GetSize(sig), GetSize(val)); + for (int i = 0; i < len; i++) { + if (rminitbits.count(sig[i])) + val[i] = State::Sx; + } + } + } + + initbits.clear(); + rminitbits.clear(); } } } diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index 15c8dc22f..0069b0570 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -60,12 +60,13 @@ code SigSpec Q = port(dff, \Q); int width = GetSize(D); - SigSpec &dffD = dff->connections_.at(\D); - SigSpec &dffQ = dff->connections_.at(\Q); - Const init; - for (const auto &b : Q) { - auto it = b.wire->attributes.find(\init); - init.bits.push_back(it == b.wire->attributes.end() ? State::Sx : it->second[b.offset]); + SigSpec dffD = dff->getPort(\D); + SigSpec dffQ = dff->getPort(\Q); + + Const initval; + for (auto b : Q) { + auto it = initbits.find(b); + initval.bits.push_back(it == initbits.end() ? State::Sx : it->second); } auto cmpx = [=](State lhs, State rhs) { @@ -76,56 +77,68 @@ code int i = width-1; while (i > 1) { - // log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]); if (D[i] != D[i-1]) break; if (!cmpx(rst[i], rst[i-1])) break; - if (!cmpx(init[i], init[i-1])) + if (!cmpx(initval[i], initval[i-1])) break; - if (!cmpx(rst[i], init[i])) + if (!cmpx(rst[i], initval[i])) break; + rminitbits.insert(Q[i]); module->connect(Q[i], Q[i-1]); i--; } if (i < width-1) { did_something = true; if (cemux) { - SigSpec &ceA = cemux->connections_.at(\A); - SigSpec &ceB = cemux->connections_.at(\B); - SigSpec &ceY = cemux->connections_.at(\Y); + SigSpec ceA = cemux->getPort(\A); + SigSpec ceB = cemux->getPort(\B); + SigSpec ceY = cemux->getPort(\Y); ceA.remove(i, width-1-i); ceB.remove(i, width-1-i); ceY.remove(i, width-1-i); + cemux->setPort(\A, ceA); + cemux->setPort(\B, ceB); + cemux->setPort(\Y, ceY); cemux->fixup_parameters(); + blacklist(cemux); } if (rstmux) { - SigSpec &rstA = rstmux->connections_.at(\A); - SigSpec &rstB = rstmux->connections_.at(\B); - SigSpec &rstY = rstmux->connections_.at(\Y); + SigSpec rstA = rstmux->getPort(\A); + SigSpec rstB = rstmux->getPort(\B); + SigSpec rstY = rstmux->getPort(\Y); rstA.remove(i, width-1-i); rstB.remove(i, width-1-i); rstY.remove(i, width-1-i); + rstmux->setPort(\A, rstA); + rstmux->setPort(\B, rstB); + rstmux->setPort(\Y, rstY); rstmux->fixup_parameters(); + blacklist(rstmux); } dffD.remove(i, width-1-i); dffQ.remove(i, width-1-i); + dff->setPort(\D, dffD); + dff->setPort(\Q, dffQ); dff->fixup_parameters(); + blacklist(dff); log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux, "n/a"), log_id(rstmux, "n/a"), width-1-i); width = i+1; } if (cemux) { - SigSpec &ceA = cemux->connections_.at(\A); - SigSpec &ceB = cemux->connections_.at(\B); - SigSpec &ceY = cemux->connections_.at(\Y); + SigSpec ceA = cemux->getPort(\A); + SigSpec ceB = cemux->getPort(\B); + SigSpec ceY = cemux->getPort(\Y); int count = 0; for (int i = width-1; i >= 0; i--) { if (D[i].wire) continue; - if (cmpx(rst[i], D[i].data) && cmpx(init[i], D[i].data)) { + if (cmpx(rst[i], D[i].data) && cmpx(initval[i], D[i].data)) { count++; + rminitbits.insert(Q[i]); module->connect(Q[i], D[i]); ceA.remove(i); ceB.remove(i); @@ -134,10 +147,21 @@ code dffQ.remove(i); } } - if (count > 0) { + if (count > 0) + { did_something = true; + + cemux->setPort(\A, ceA); + cemux->setPort(\B, ceB); + cemux->setPort(\Y, ceY); cemux->fixup_parameters(); + blacklist(cemux); + + dff->setPort(\D, dffD); + dff->setPort(\Q, dffQ); dff->fixup_parameters(); + blacklist(dff); + log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), log_id(rstmux, "n/a"), count); } } From 2ae7dec5300bb61a90842fefb1e846cd9f667a9e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 9 Sep 2019 08:33:26 +0300 Subject: [PATCH 092/123] Add tests for Xilinx UG901 examples --- Makefile | 1 + tests/xilinx_ug901/asym_ram_sdp_read_wider.v | 74 +++++++++++ tests/xilinx_ug901/asym_ram_sdp_read_wider.ys | 22 ++++ tests/xilinx_ug901/asym_ram_sdp_write_wider.v | 75 +++++++++++ .../xilinx_ug901/asym_ram_sdp_write_wider.ys | 31 +++++ tests/xilinx_ug901/asym_ram_tdp_read_first.v | 85 ++++++++++++ tests/xilinx_ug901/asym_ram_tdp_read_first.ys | 21 +++ tests/xilinx_ug901/asym_ram_tdp_write_first.v | 92 +++++++++++++ .../xilinx_ug901/asym_ram_tdp_write_first.ys | 29 +++++ tests/xilinx_ug901/black_box_1.v | 19 +++ tests/xilinx_ug901/black_box_1.ys | 15 +++ tests/xilinx_ug901/bytewrite_ram_1b.v | 42 ++++++ tests/xilinx_ug901/bytewrite_ram_1b.ys | 22 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_nc.v | 78 +++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys | 22 ++++ .../bytewrite_tdp_ram_readfirst2.v | 71 ++++++++++ .../bytewrite_tdp_ram_readfirst2.ys | 21 +++ tests/xilinx_ug901/bytewrite_tdp_ram_rf.v | 61 +++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys | 21 +++ tests/xilinx_ug901/bytewrite_tdp_ram_wf.v | 68 ++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys | 23 ++++ tests/xilinx_ug901/cmacc.v | 122 ++++++++++++++++++ tests/xilinx_ug901/cmacc.ys | 25 ++++ tests/xilinx_ug901/cmult.v | 71 ++++++++++ tests/xilinx_ug901/cmult.ys | 31 +++++ .../xilinx_ug901/dynamic_shift_registers_1.v | 21 +++ .../xilinx_ug901/dynamic_shift_registers_1.ys | 15 +++ tests/xilinx_ug901/dynpreaddmultadd.v | 47 +++++++ tests/xilinx_ug901/dynpreaddmultadd.ys | 31 +++++ tests/xilinx_ug901/fsm_1.v | 42 ++++++ tests/xilinx_ug901/fsm_1.ys | 16 +++ tests/xilinx_ug901/latches.v | 17 +++ tests/xilinx_ug901/latches.ys | 10 ++ tests/xilinx_ug901/macc.v | 47 +++++++ tests/xilinx_ug901/macc.ys | 23 ++++ tests/xilinx_ug901/mult_unsigned.v | 33 +++++ tests/xilinx_ug901/mult_unsigned.ys | 29 +++++ tests/xilinx_ug901/presubmult.v | 43 ++++++ tests/xilinx_ug901/presubmult.ys | 23 ++++ .../xilinx_ug901/ram_simple_dual_one_clock.v | 25 ++++ .../xilinx_ug901/ram_simple_dual_one_clock.ys | 20 +++ .../xilinx_ug901/ram_simple_dual_two_clocks.v | 30 +++++ .../ram_simple_dual_two_clocks.ys | 20 +++ tests/xilinx_ug901/rams_dist.v | 24 ++++ tests/xilinx_ug901/rams_dist.ys | 21 +++ tests/xilinx_ug901/rams_init_file.data | 64 +++++++++ tests/xilinx_ug901/rams_init_file.v | 24 ++++ tests/xilinx_ug901/rams_init_file.ys | 22 ++++ tests/xilinx_ug901/rams_pipeline.v | 42 ++++++ tests/xilinx_ug901/rams_pipeline.ys | 22 ++++ tests/xilinx_ug901/rams_sp_nc.v | 26 ++++ tests/xilinx_ug901/rams_sp_nc.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rf.v | 26 ++++ tests/xilinx_ug901/rams_sp_rf.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rf_rst.v | 29 +++++ tests/xilinx_ug901/rams_sp_rf_rst.ys | 28 ++++ tests/xilinx_ug901/rams_sp_rom.v | 46 +++++++ tests/xilinx_ug901/rams_sp_rom.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rom_1.v | 53 ++++++++ tests/xilinx_ug901/rams_sp_rom_1.ys | 22 ++++ tests/xilinx_ug901/rams_sp_wf.v | 26 ++++ tests/xilinx_ug901/rams_sp_wf.ys | 26 ++++ tests/xilinx_ug901/rams_tdp_rf_rf.v | 33 +++++ tests/xilinx_ug901/rams_tdp_rf_rf.ys | 21 +++ tests/xilinx_ug901/registers_1.v | 25 ++++ tests/xilinx_ug901/registers_1.ys | 12 ++ tests/xilinx_ug901/run-test.sh | 20 +++ tests/xilinx_ug901/sfir_shifter.v | 19 +++ tests/xilinx_ug901/sfir_shifter.ys | 16 +++ tests/xilinx_ug901/shift_registers_0.v | 22 ++++ tests/xilinx_ug901/shift_registers_0.ys | 13 ++ tests/xilinx_ug901/shift_registers_1.v | 24 ++++ tests/xilinx_ug901/shift_registers_1.ys | 14 ++ tests/xilinx_ug901/squarediffmacc.v | 52 ++++++++ tests/xilinx_ug901/squarediffmacc.ys | 23 ++++ tests/xilinx_ug901/squarediffmult.v | 42 ++++++ tests/xilinx_ug901/squarediffmult.ys | 30 +++++ tests/xilinx_ug901/top_mux.v | 18 +++ tests/xilinx_ug901/top_mux.ys | 13 ++ tests/xilinx_ug901/tristates_1.v | 17 +++ tests/xilinx_ug901/tristates_1.ys | 13 ++ tests/xilinx_ug901/tristates_2.v | 10 ++ tests/xilinx_ug901/tristates_2.ys | 13 ++ .../xilinx_ultraram_single_port_no_change.v | 78 +++++++++++ .../xilinx_ultraram_single_port_no_change.ys | 25 ++++ .../xilinx_ultraram_single_port_read_first.v | 78 +++++++++++ .../xilinx_ultraram_single_port_read_first.ys | 24 ++++ .../xilinx_ultraram_single_port_write_first.v | 82 ++++++++++++ ...xilinx_ultraram_single_port_write_first.ys | 24 ++++ 89 files changed, 2962 insertions(+) create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.v create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.v create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.ys create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.v create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.ys create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.v create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.ys create mode 100644 tests/xilinx_ug901/black_box_1.v create mode 100644 tests/xilinx_ug901/black_box_1.ys create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.v create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_rf.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_wf.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys create mode 100644 tests/xilinx_ug901/cmacc.v create mode 100644 tests/xilinx_ug901/cmacc.ys create mode 100644 tests/xilinx_ug901/cmult.v create mode 100644 tests/xilinx_ug901/cmult.ys create mode 100644 tests/xilinx_ug901/dynamic_shift_registers_1.v create mode 100644 tests/xilinx_ug901/dynamic_shift_registers_1.ys create mode 100644 tests/xilinx_ug901/dynpreaddmultadd.v create mode 100644 tests/xilinx_ug901/dynpreaddmultadd.ys create mode 100644 tests/xilinx_ug901/fsm_1.v create mode 100644 tests/xilinx_ug901/fsm_1.ys create mode 100644 tests/xilinx_ug901/latches.v create mode 100644 tests/xilinx_ug901/latches.ys create mode 100644 tests/xilinx_ug901/macc.v create mode 100644 tests/xilinx_ug901/macc.ys create mode 100644 tests/xilinx_ug901/mult_unsigned.v create mode 100644 tests/xilinx_ug901/mult_unsigned.ys create mode 100644 tests/xilinx_ug901/presubmult.v create mode 100644 tests/xilinx_ug901/presubmult.ys create mode 100644 tests/xilinx_ug901/ram_simple_dual_one_clock.v create mode 100644 tests/xilinx_ug901/ram_simple_dual_one_clock.ys create mode 100644 tests/xilinx_ug901/ram_simple_dual_two_clocks.v create mode 100644 tests/xilinx_ug901/ram_simple_dual_two_clocks.ys create mode 100644 tests/xilinx_ug901/rams_dist.v create mode 100644 tests/xilinx_ug901/rams_dist.ys create mode 100644 tests/xilinx_ug901/rams_init_file.data create mode 100644 tests/xilinx_ug901/rams_init_file.v create mode 100644 tests/xilinx_ug901/rams_init_file.ys create mode 100644 tests/xilinx_ug901/rams_pipeline.v create mode 100644 tests/xilinx_ug901/rams_pipeline.ys create mode 100644 tests/xilinx_ug901/rams_sp_nc.v create mode 100644 tests/xilinx_ug901/rams_sp_nc.ys create mode 100644 tests/xilinx_ug901/rams_sp_rf.v create mode 100644 tests/xilinx_ug901/rams_sp_rf.ys create mode 100644 tests/xilinx_ug901/rams_sp_rf_rst.v create mode 100644 tests/xilinx_ug901/rams_sp_rf_rst.ys create mode 100644 tests/xilinx_ug901/rams_sp_rom.v create mode 100644 tests/xilinx_ug901/rams_sp_rom.ys create mode 100644 tests/xilinx_ug901/rams_sp_rom_1.v create mode 100644 tests/xilinx_ug901/rams_sp_rom_1.ys create mode 100644 tests/xilinx_ug901/rams_sp_wf.v create mode 100644 tests/xilinx_ug901/rams_sp_wf.ys create mode 100644 tests/xilinx_ug901/rams_tdp_rf_rf.v create mode 100644 tests/xilinx_ug901/rams_tdp_rf_rf.ys create mode 100644 tests/xilinx_ug901/registers_1.v create mode 100644 tests/xilinx_ug901/registers_1.ys create mode 100755 tests/xilinx_ug901/run-test.sh create mode 100644 tests/xilinx_ug901/sfir_shifter.v create mode 100644 tests/xilinx_ug901/sfir_shifter.ys create mode 100644 tests/xilinx_ug901/shift_registers_0.v create mode 100644 tests/xilinx_ug901/shift_registers_0.ys create mode 100644 tests/xilinx_ug901/shift_registers_1.v create mode 100644 tests/xilinx_ug901/shift_registers_1.ys create mode 100644 tests/xilinx_ug901/squarediffmacc.v create mode 100644 tests/xilinx_ug901/squarediffmacc.ys create mode 100644 tests/xilinx_ug901/squarediffmult.v create mode 100644 tests/xilinx_ug901/squarediffmult.ys create mode 100644 tests/xilinx_ug901/top_mux.v create mode 100644 tests/xilinx_ug901/top_mux.ys create mode 100644 tests/xilinx_ug901/tristates_1.v create mode 100644 tests/xilinx_ug901/tristates_1.ys create mode 100644 tests/xilinx_ug901/tristates_2.v create mode 100644 tests/xilinx_ug901/tristates_2.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys diff --git a/Makefile b/Makefile index 895cfbf89..ef02bc947 100644 --- a/Makefile +++ b/Makefile @@ -715,6 +715,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh + +cd tests/xilinx_ug901 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v new file mode 100644 index 000000000..0716dffdc --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v @@ -0,0 +1,74 @@ +// Asymmetric port RAM +// Read Wider than Write. Read Statement in loop +//asym_ram_sdp_read_wider.v + +module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); +parameter WIDTHA = 4; +parameter SIZEA = 1024; +parameter ADDRWIDTHA = 10; + +parameter WIDTHB = 16; +parameter SIZEB = 256; +parameter ADDRWIDTHB = 8; +input clkA; +input clkB; +input weA; +input enaA, enaB; +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +output [WIDTHB-1:0] doB; +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHB-1:0] readB; + +always @(posedge clkA) +begin + if (enaA) begin + if (weA) + RAM[addrA] <= diA; + end +end + + +always @(posedge clkB) +begin : ramread + integer i; + reg [log2RATIO-1:0] lsbaddr; + if (enaB) begin + for (i = 0; i < RATIO; i = i+1) begin + lsbaddr = i; + readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; + end + end +end +assign doB = readB; + +endmodule + diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys new file mode 100644 index 000000000..c63157cdf --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys @@ -0,0 +1,22 @@ +read_verilog asym_ram_sdp_read_wider.v +hierarchy -top asym_ram_sdp_read_wider +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_sdp_read_wider +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 1 t:LUT2 +select -assert-count 4 t:RAMB18E1 + +select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v new file mode 100644 index 000000000..22d12d2ce --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v @@ -0,0 +1,75 @@ +// Asymmetric port RAM +// Write wider than Read. Write Statement in a loop. +// asym_ram_sdp_write_wider.v + +module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); +parameter WIDTHB = 4; +//Default parameters were changed because of slow test +//parameter SIZEB = 1024; +//parameter ADDRWIDTHB = 10; +parameter SIZEB = 256; +parameter ADDRWIDTHB = 8; + +//parameter WIDTHA = 16; +parameter WIDTHA = 8; +parameter SIZEA = 256; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA; +input enaA, enaB; +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +output [WIDTHB-1:0] doB; +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) begin + if (enaB) begin + readB <= RAM[addrB]; + end +end +assign doB = readB; + +always @(posedge clkA) +begin : ramwrite + integer i; + reg [log2RATIO-1:0] lsbaddr; + for (i=0; i< RATIO; i= i+ 1) begin : write1 + lsbaddr = i; + if (enaA) begin + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end +end + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys new file mode 100644 index 000000000..229d98df6 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys @@ -0,0 +1,31 @@ +read_verilog asym_ram_sdp_write_wider.v +hierarchy -top asym_ram_sdp_write_wider +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_sdp_write_wider +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 1028 t:FDRE +select -assert-count 170 t:LUT2 +select -assert-count 6 t:LUT3 +select -assert-count 518 t:LUT4 +select -assert-count 10 t:LUT5 +select -assert-count 484 t:LUT6 +select -assert-count 157 t:MUXF7 +select -assert-count 3 t:MUXF8 + +#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4 +#select -assert-count 8 t:RAM128X1D + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v new file mode 100644 index 000000000..2b807a382 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.v @@ -0,0 +1,85 @@ +// Asymetric RAM - TDP +// READ_FIRST MODE. +// asym_ram_tdp_read_first.v + + +module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); +parameter WIDTHB = 4; +parameter SIZEB = 1024; +parameter ADDRWIDTHB = 10; +parameter WIDTHA = 16; +parameter SIZEA = 256; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA, weB; +input enaA, enaB; + +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +input [WIDTHB-1:0] diB; + +output [WIDTHA-1:0] doA; +output [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHA-1:0] readA; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) +begin + if (enaB) begin + readB <= RAM[addrB] ; + if (weB) + RAM[addrB] <= diB; + end +end + + +always @(posedge clkA) +begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i=0; i< RATIO; i= i+ 1) begin + lsbaddr = i; + if (enaA) begin + readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}]; + + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end +end + +assign doA = readA; +assign doB = readB; + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys new file mode 100644 index 000000000..5f96b800c --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys @@ -0,0 +1,21 @@ +read_verilog asym_ram_tdp_read_first.v +hierarchy -top asym_ram_tdp_read_first +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_tdp_read_first +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 1 t:$mem +select -assert-count 2 t:LUT2 + +select -assert-none t:$mem t:LUT2 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v new file mode 100644 index 000000000..90187ea26 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.v @@ -0,0 +1,92 @@ +// Asymmetric port RAM - TDP +// WRITE_FIRST MODE. +// asym_ram_tdp_write_first.v + + +module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); +parameter WIDTHB = 4; +//Default parameters were changed because of slow test +//parameter SIZEB = 1024; +//parameter ADDRWIDTHB = 10; +parameter SIZEB = 32; +parameter ADDRWIDTHB = 8; + +//parameter WIDTHA = 16; +parameter WIDTHA = 4; +//parameter SIZEA = 256; +parameter SIZEA = 32; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA, weB; +input enaA, enaB; + +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +input [WIDTHB-1:0] diB; + +output [WIDTHA-1:0] doA; +output [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHA-1:0] readA; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) +begin + if (enaB) begin + if (weB) + RAM[addrB] = diB; + readB = RAM[addrB] ; + end +end + + +always @(posedge clkA) +begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i=0; i< RATIO; i= i+ 1) begin + lsbaddr = i; + if (enaA) begin + + if (weA) + RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH]; + + readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}]; + end + end +end + +assign doA = readA; +assign doB = readB; + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys new file mode 100644 index 000000000..bbe3cc849 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys @@ -0,0 +1,29 @@ +read_verilog asym_ram_tdp_write_first.v +hierarchy -top asym_ram_tdp_write_first +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_tdp_write_first +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 200 t:FDRE +select -assert-count 10 t:LUT2 +select -assert-count 44 t:LUT3 +select -assert-count 81 t:LUT4 +select -assert-count 104 t:LUT5 +select -assert-count 560 t:LUT6 +select -assert-count 261 t:MUXF7 +select -assert-count 127 t:MUXF8 + + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v new file mode 100644 index 000000000..40caa1b10 --- /dev/null +++ b/tests/xilinx_ug901/black_box_1.v @@ -0,0 +1,19 @@ +// Black Box +// black_box_1.v +// +(* black_box *) module black_box1 (in1, in2, dout); +input in1, in2; +output dout; +endmodule + +module black_box_1 (DI_1, DI_2, DOUT); +input DI_1, DI_2; +output DOUT; + +black_box1 U1 ( + .in1(DI_1), + .in2(DI_2), + .dout(DOUT) + ); + +endmodule diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys new file mode 100644 index 000000000..acf0b5761 --- /dev/null +++ b/tests/xilinx_ug901/black_box_1.ys @@ -0,0 +1,15 @@ +read_verilog black_box_1.v +hierarchy -top black_box_1 +proc +tribuf +flatten +synth +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd black_box_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 black box. +#stat +#select -assert-count 0 t:LUT1 +#select -assert-count 1 t:$_TBUF_ +#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v new file mode 100644 index 000000000..46d86c297 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_ram_1b.v @@ -0,0 +1,42 @@ +// Single-Port BRAM with Byte-wide Write Enable +// Read-First mode +// Single-process description +// Compact description of the write with a generate-for +// statement +// Column width and number of columns easily configurable +// +// bytewrite_ram_1b.v +// + +module bytewrite_ram_1b (clk, we, addr, di, do); + +parameter SIZE = 1024; +parameter ADDR_WIDTH = 10; +parameter COL_WIDTH = 8; +parameter NB_COL = 4; + +input clk; +input [NB_COL-1:0] we; +input [ADDR_WIDTH-1:0] addr; +input [NB_COL*COL_WIDTH-1:0] di; +output reg [NB_COL*COL_WIDTH-1:0] do; + +reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; + +always @(posedge clk) +begin + do <= RAM[addr]; +end + +generate genvar i; +for (i = 0; i < NB_COL; i = i+1) +begin +always @(posedge clk) +begin + if (we[i]) + RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; + end +end +endgenerate + +endmodule diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys new file mode 100644 index 000000000..4f0967801 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_ram_1b.ys @@ -0,0 +1,22 @@ +read_verilog bytewrite_ram_1b.v +hierarchy -top bytewrite_ram_1b +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd bytewrite_ram_1b +stat +#Vivado synthesizes 1 RAMB36E1. +select -assert-count 1 t:BUFG +select -assert-count 32 t:LUT2 +select -assert-count 8 t:RAMB36E1 + +select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v new file mode 100644 index 000000000..1093b0838 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v @@ -0,0 +1,78 @@ +// +// True-Dual-Port BRAM with Byte-wide Write Enable +// No-Change mode +// +// bytewrite_tdp_ram_nc.v +// +// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended +module bytewrite_tdp_ram_nc + #( + //--------------------------------------------------------------- + parameter NUM_COL = 4, + parameter COL_WIDTH = 8, + parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth + parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits + //--------------------------------------------------------------- + ) ( + input clkA, + input enaA, + input [NUM_COL-1:0] weA, + input [ADDR_WIDTH-1:0] addrA, + input [DATA_WIDTH-1:0] dinA, + output reg [DATA_WIDTH-1:0] doutA, + + input clkB, + input enaB, + input [NUM_COL-1:0] weB, + input [ADDR_WIDTH-1:0] addrB, + input [DATA_WIDTH-1:0] dinB, + output reg [DATA_WIDTH-1:0] doutB + ); + + + // Core Memory + reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; + + // Port-A Operation + generate + genvar i; + for(i=0;i run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v new file mode 100644 index 000000000..a8b144bcd --- /dev/null +++ b/tests/xilinx_ug901/sfir_shifter.v @@ -0,0 +1,19 @@ +//sfir_shifter.v +(* dont_touch = "yes" *) +module sfir_shifter #(parameter dsize = 16, nbtap = 4) + (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout); + + (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1]; + integer i; + + always @(posedge clk) + begin + tmp[0] <= datain; + for (i=0; i<=2*nbtap-2; i=i+1) + tmp[i+1] <= tmp[i]; + end + + assign dataout = tmp[2*nbtap-1]; + +endmodule +// sfir_shifter diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys new file mode 100644 index 000000000..b9fbeb8cb --- /dev/null +++ b/tests/xilinx_ug901/sfir_shifter.ys @@ -0,0 +1,16 @@ +read_verilog sfir_shifter.v +hierarchy -top sfir_shifter +proc +flatten +#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd sfir_shifter +#Vivado synthesizes 32 FDRE, 16 SRL16E. +stat +select -assert-count 1 t:BUFG +select -assert-count 16 t:SRL16E + +select -assert-none t:BUFG t:SRL16E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v new file mode 100644 index 000000000..77a3ec893 --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_0.v @@ -0,0 +1,22 @@ +// 8-bit Shift Register +// Rising edge clock +// Active high clock enable +// Concatenation-based template +// File: shift_registers_0.v + +module shift_registers_0 (clk, clken, SI, SO); +parameter WIDTH = 32; +input clk, clken, SI; +output SO; + +reg [WIDTH-1:0] shreg; + +always @(posedge clk) + begin + if (clken) + shreg = {shreg[WIDTH-2:0], SI}; + end + +assign SO = shreg[WIDTH-1]; + +endmodule diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys new file mode 100644 index 000000000..ae7d23a7f --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_0.ys @@ -0,0 +1,13 @@ +read_verilog shift_registers_0.v +hierarchy -top shift_registers_0 +proc +flatten +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd shift_registers_0 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. +select -assert-count 1 t:BUFG +select -assert-count 1 t:SRLC32E +select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v new file mode 100644 index 000000000..d50820e7b --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_1.v @@ -0,0 +1,24 @@ +// 32-bit Shift Register +// Rising edge clock +// Active high clock enable +// For-loop based template +// File: shift_registers_1.v + +module shift_registers_1 (clk, clken, SI, SO); +parameter WIDTH = 32; +input clk, clken, SI; +output SO; +reg [WIDTH-1:0] shreg; + +integer i; +always @(posedge clk) +begin + if (clken) + begin + for (i = 0; i < WIDTH-1; i = i+1) + shreg[i+1] <= shreg[i]; + shreg[0] <= SI; + end +end +assign SO = shreg[WIDTH-1]; +endmodule diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys new file mode 100644 index 000000000..fb935c446 --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_1.ys @@ -0,0 +1,14 @@ +read_verilog shift_registers_1.v +hierarchy -top shift_registers_1 +proc +flatten + +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd shift_registers_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. +select -assert-count 1 t:BUFG +select -assert-count 1 t:SRLC32E +select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v new file mode 100644 index 000000000..6535b24c4 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmacc.v @@ -0,0 +1,52 @@ +// This module performs subtraction of two inputs, squaring on the diff +// and then accumulation +// This can be implemented in 1 DSP Block (Ultrascale architecture) +// File : squarediffmacc.v +module squarediffmacc # ( + //Default parameters were changed because of slow test + //parameter SIZEIN = 16, + //SIZEOUT = 40 + parameter SIZEIN = 8, + SIZEOUT = 20 + ) + ( + input clk, + input ce, + input sload, + input signed [SIZEIN-1:0] a, + input signed [SIZEIN-1:0] b, + output signed [SIZEOUT+1:0] accum_out + ); + +// Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN:0] diff_reg; +reg sload_reg; +reg signed [2*SIZEIN+1:0] m_reg; +reg signed [SIZEOUT-1:0] adder_out, old_result; + + always @(sload_reg or adder_out) + if (sload_reg) + old_result <= 0; + else + // 'sload' is now and opens the accumulation loop. + // The accumulator takes the next multiplier output + // in the same cycle. + old_result <= adder_out; + + always @(posedge clk) + if (ce) + begin + a_reg <= a; + b_reg <= b; + diff_reg <= a_reg - b_reg; + m_reg <= diff_reg * diff_reg; + sload_reg <= sload; + // Store accumulation result into a register + adder_out <= old_result + m_reg; + end + + // Output accumulation result + assign accum_out = adder_out; + +endmodule // squarediffmacc diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys new file mode 100644 index 000000000..92474bea3 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmacc.ys @@ -0,0 +1,23 @@ +read_verilog squarediffmacc.v +hierarchy -top squarediffmacc +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd squarediffmacc +#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT. +stat +select -assert-count 1 t:BUFG +select -assert-count 64 t:FDRE +select -assert-count 78 t:LUT2 +select -assert-count 7 t:LUT3 +select -assert-count 11 t:LUT4 +select -assert-count 8 t:LUT5 +select -assert-count 125 t:LUT6 +select -assert-count 44 t:MUXCY +select -assert-count 50 t:MUXF7 +select -assert-count 17 t:MUXF8 +select -assert-count 47 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v new file mode 100644 index 000000000..0f41b67bc --- /dev/null +++ b/tests/xilinx_ug901/squarediffmult.v @@ -0,0 +1,42 @@ +// Squarer support for DSP block (DSP48E2) with +// pre-adder configured +// as subtractor +// File: squarediffmult.v + +module squarediffmult # (parameter SIZEIN = 16) + ( + input clk, ce, rst, + input signed [SIZEIN-1:0] a, b, + output signed [2*SIZEIN+1:0] square_out + ); + + // Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN:0] diff_reg; +reg signed [2*SIZEIN+1:0] m_reg, p_reg; + +always @(posedge clk) +begin + if (rst) + begin + a_reg <= 0; + b_reg <= 0; + diff_reg <= 0; + m_reg <= 0; + p_reg <= 0; + end + else + if (ce) + begin + a_reg <= a; + b_reg <= b; + diff_reg <= a_reg - b_reg; + m_reg <= diff_reg * diff_reg; + p_reg <= m_reg; + end +end + +// Output result +assign square_out = p_reg; + +endmodule // squarediffmult diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys new file mode 100644 index 000000000..3468e5bb4 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmult.ys @@ -0,0 +1,30 @@ +read_verilog squarediffmult.v +hierarchy -top squarediffmult +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd squarediffmult +stat +#Vivado synthesizes 16 FDRE, 1 DSP48E1. +select -assert-count 1 t:BUFG +select -assert-count 117 t:FDRE +select -assert-count 223 t:LUT2 +select -assert-count 50 t:LUT3 +select -assert-count 38 t:LUT4 +select -assert-count 56 t:LUT5 +select -assert-count 372 t:LUT6 +select -assert-count 49 t:MUXCY +select -assert-count 99 t:MUXF7 +select -assert-count 26 t:MUXF8 +select -assert-count 51 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v new file mode 100644 index 000000000..c23c7491c --- /dev/null +++ b/tests/xilinx_ug901/top_mux.v @@ -0,0 +1,18 @@ +// Multiplexer using case statement +module mux4 (sel, a, b, c, d, outmux); +input [1:0] sel; +input [1:0] a, b, c, d; +output [1:0] outmux; +reg [1:0] outmux; + +always @ * + begin + case(sel) + 2'b00 : outmux = a; + 2'b01 : outmux = b; + 2'b10 : outmux = c; + 2'b11 : outmux = d; + endcase + end +endmodule + diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys new file mode 100644 index 000000000..0245f3bbc --- /dev/null +++ b/tests/xilinx_ug901/top_mux.ys @@ -0,0 +1,13 @@ +read_verilog top_mux.v +hierarchy -top mux4 +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd mux4 +#Vivado synthesizes 2 LUT. +stat +select -assert-count 2 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v new file mode 100644 index 000000000..0038a9989 --- /dev/null +++ b/tests/xilinx_ug901/tristates_1.v @@ -0,0 +1,17 @@ +// Tristate Description Using Combinatorial Always Block +// File: tristates_1.v +// +module tristates_1 (T, I, O); +input T, I; +output O; +reg O; + +always @(T or I) +begin + if (~T) + O = I; + else + O = 1'bZ; +end + +endmodule diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys new file mode 100644 index 000000000..7c13dc227 --- /dev/null +++ b/tests/xilinx_ug901/tristates_1.ys @@ -0,0 +1,13 @@ +read_verilog tristates_1.v +hierarchy -top tristates_1 +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristates_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 3 IBUF, 1 OBUFT. +select -assert-count 1 t:LUT1 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v new file mode 100644 index 000000000..0c70a1257 --- /dev/null +++ b/tests/xilinx_ug901/tristates_2.v @@ -0,0 +1,10 @@ +// Tristate Description Using Concurrent Assignment +// File: tristates_2.v +// +module tristates_2 (T, I, O); +input T, I; +output O; + +assign O = (~T) ? I: 1'bZ; + +endmodule diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys new file mode 100644 index 000000000..ba2e1d855 --- /dev/null +++ b/tests/xilinx_ug901/tristates_2.ys @@ -0,0 +1,13 @@ +read_verilog tristates_2.v +hierarchy -top tristates_2 +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristates_2 # Constrain all select calls below inside the top module +#Vivado synthesizes 3 IBUF, 1 OBUFT. +select -assert-count 1 t:LUT1 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v new file mode 100644 index 000000000..f5e843dc9 --- /dev/null +++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v @@ -0,0 +1,78 @@ +// Xilinx UltraRAM Single Port No Change Mode. This code implements +// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is +// when data is written, the output of RAM is unchanged. Only when write is +// inactive data corresponding to the address is presented on the output port. +// +module xilinx_ultraram_single_port_no_change #( +//Default parameters were changed because of slow test + //parameter AWIDTH = 12, // Address Width + //parameter DWIDTH = 72, // Data Width + //parameter NBPIPE = 3 // Number of pipeline Registers + parameter AWIDTH = 8, // Address Width + parameter DWIDTH = 8, // Data Width + parameter NBPIPE = 3 // Number of pipeline Registers + ) ( + input clk, // Clock + input rst, // Reset + input we, // Write Enable + input regce, // Output Register Enable + input mem_en, // Memory Enable + input [DWIDTH-1:0] din, // Data Input + input [AWIDTH-1:0] addr, // Address Input + output reg [DWIDTH-1:0] dout // Data Output + ); + +(* ram_style = "ultra" *) +reg [DWIDTH-1:0] mem[(1< Date: Mon, 9 Sep 2019 08:49:29 +0300 Subject: [PATCH 093/123] Add comments for unproven cells. --- tests/xilinx_ug901/dynamic_shift_registers_1.ys | 2 +- tests/xilinx_ug901/shift_registers_0.ys | 1 + tests/xilinx_ug901/shift_registers_1.ys | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/xilinx_ug901/dynamic_shift_registers_1.ys b/tests/xilinx_ug901/dynamic_shift_registers_1.ys index 994e12a3e..f70c84f2f 100644 --- a/tests/xilinx_ug901/dynamic_shift_registers_1.ys +++ b/tests/xilinx_ug901/dynamic_shift_registers_1.ys @@ -2,7 +2,7 @@ read_verilog dynamic_shift_registers_1.v hierarchy -top dynamic_shift_register_1 proc flatten - +#ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys index ae7d23a7f..89da1d7cc 100644 --- a/tests/xilinx_ug901/shift_registers_0.ys +++ b/tests/xilinx_ug901/shift_registers_0.ys @@ -2,6 +2,7 @@ read_verilog shift_registers_0.v hierarchy -top shift_registers_0 proc flatten +#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys index fb935c446..b53b6cb25 100644 --- a/tests/xilinx_ug901/shift_registers_1.ys +++ b/tests/xilinx_ug901/shift_registers_1.ys @@ -2,7 +2,7 @@ read_verilog shift_registers_1.v hierarchy -top shift_registers_1 proc flatten - +#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check From 757c476f625bef871f9a4388d4d19bf8c3bc400b Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 10 Sep 2019 08:08:03 +0300 Subject: [PATCH 094/123] Add smoke tests to tests/xilinx --- Makefile | 1 + tests/xilinx/add_sub.v | 13 +++++ tests/xilinx/add_sub.ys | 10 ++++ tests/xilinx/adffs.v | 91 +++++++++++++++++++++++++++++++++++ tests/xilinx/adffs.ys | 14 ++++++ tests/xilinx/alu.v | 19 ++++++++ tests/xilinx/alu.ys | 21 ++++++++ tests/xilinx/counter.v | 17 +++++++ tests/xilinx/counter.ys | 14 ++++++ tests/xilinx/dffs.v | 37 +++++++++++++++ tests/xilinx/dffs.ys | 10 ++++ tests/xilinx/div_mod.v | 13 +++++ tests/xilinx/div_mod.ys | 17 +++++++ tests/xilinx/fsm.v | 73 ++++++++++++++++++++++++++++ tests/xilinx/fsm.ys | 14 ++++++ tests/xilinx/latches.v | 6 +-- tests/xilinx/latches.ys | 19 +++++--- tests/xilinx/logic.v | 18 +++++++ tests/xilinx/logic.ys | 10 ++++ tests/xilinx/memory.v | 21 ++++++++ tests/xilinx/memory.ys | 17 +++++++ tests/xilinx/mul.v | 11 +++++ tests/xilinx/mul.ys | 15 ++++++ tests/xilinx/mux.v | 100 +++++++++++++++++++++++++++++++++++++++ tests/xilinx/mux.ys | 10 ++++ tests/xilinx/run-test.sh | 2 +- tests/xilinx/shifter.v | 22 +++++++++ tests/xilinx/shifter.ys | 11 +++++ tests/xilinx/tribuf.v | 29 ++++++++++++ tests/xilinx/tribuf.ys | 11 +++++ 30 files changed, 656 insertions(+), 10 deletions(-) create mode 100644 tests/xilinx/add_sub.v create mode 100644 tests/xilinx/add_sub.ys create mode 100644 tests/xilinx/adffs.v create mode 100644 tests/xilinx/adffs.ys create mode 100644 tests/xilinx/alu.v create mode 100644 tests/xilinx/alu.ys create mode 100644 tests/xilinx/counter.v create mode 100644 tests/xilinx/counter.ys create mode 100644 tests/xilinx/dffs.v create mode 100644 tests/xilinx/dffs.ys create mode 100644 tests/xilinx/div_mod.v create mode 100644 tests/xilinx/div_mod.ys create mode 100644 tests/xilinx/fsm.v create mode 100644 tests/xilinx/fsm.ys create mode 100644 tests/xilinx/logic.v create mode 100644 tests/xilinx/logic.ys create mode 100644 tests/xilinx/memory.v create mode 100644 tests/xilinx/memory.ys create mode 100644 tests/xilinx/mul.v create mode 100644 tests/xilinx/mul.ys create mode 100644 tests/xilinx/mux.v create mode 100644 tests/xilinx/mux.ys create mode 100644 tests/xilinx/shifter.v create mode 100644 tests/xilinx/shifter.ys create mode 100644 tests/xilinx/tribuf.v create mode 100644 tests/xilinx/tribuf.ys diff --git a/Makefile b/Makefile index ef02bc947..82af448da 100644 --- a/Makefile +++ b/Makefile @@ -715,6 +715,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh + +cd tests/xilinx && bash run-test.sh $(SEEDOPT) +cd tests/xilinx_ug901 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." diff --git a/tests/xilinx/add_sub.v b/tests/xilinx/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/xilinx/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys new file mode 100644 index 000000000..821341f20 --- /dev/null +++ b/tests/xilinx/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 14 t:LUT2 +select -assert-count 6 t:MUXCY +select -assert-count 8 t:XORCY +select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D + diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/xilinx/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys new file mode 100644 index 000000000..96d8e176f --- /dev/null +++ b/tests/xilinx/adffs.ys @@ -0,0 +1,14 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 3 t:FDRE +select -assert-count 1 t:FDRE_1 +select -assert-count 4 t:LUT2 +select -assert-count 4 t:LUT3 +select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/xilinx/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys new file mode 100644 index 000000000..f85f03928 --- /dev/null +++ b/tests/xilinx/alu.ys @@ -0,0 +1,21 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + + +select -assert-count 1 t:BUFG +select -assert-count 32 t:LUT1 +select -assert-count 142 t:LUT2 +select -assert-count 55 t:LUT3 +select -assert-count 70 t:LUT4 +select -assert-count 46 t:LUT5 +select -assert-count 625 t:LUT6 +select -assert-count 62 t:MUXCY +select -assert-count 265 t:MUXF7 +select -assert-count 79 t:MUXF8 +select -assert-count 64 t:XORCY +select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/counter.v b/tests/xilinx/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/xilinx/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys new file mode 100644 index 000000000..b602b74d7 --- /dev/null +++ b/tests/xilinx/counter.ys @@ -0,0 +1,14 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDCE +select -assert-count 1 t:LUT1 +select -assert-count 7 t:MUXCY +select -assert-count 8 t:XORCY +select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/xilinx/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys new file mode 100644 index 000000000..6a98994c0 --- /dev/null +++ b/tests/xilinx/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 2 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/xilinx/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys new file mode 100644 index 000000000..cc00b1a27 --- /dev/null +++ b/tests/xilinx/div_mod.ys @@ -0,0 +1,17 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 12 t:LUT1 +select -assert-count 21 t:LUT2 +select -assert-count 13 t:LUT4 +select -assert-count 6 t:LUT5 +select -assert-count 80 t:LUT6 +select -assert-count 65 t:MUXCY +select -assert-count 36 t:MUXF7 +select -assert-count 9 t:MUXF8 +select -assert-count 28 t:XORCY +select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/xilinx/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys new file mode 100644 index 000000000..3b73891c2 --- /dev/null +++ b/tests/xilinx/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 5 t:FDRE +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT4 +select -assert-count 4 t:LUT6 +select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v index 83bad7f35..9dc43e4c2 100644 --- a/tests/xilinx/latches.v +++ b/tests/xilinx/latches.v @@ -1,19 +1,19 @@ module latchp - ( input d, en, output reg q ); + ( input d, clk, en, output reg q ); always @* if ( en ) q <= d; endmodule module latchn - ( input d, en, output reg q ); + ( input d, clk, en, output reg q ); always @* if ( !en ) q <= d; endmodule module latchsr - ( input d, en, clr, pre, output reg q ); + ( input d, clk, en, clr, pre, output reg q ); always @* if ( clr ) q <= 1'b0; diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index bd1dffd21..9ab562bcf 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -1,13 +1,20 @@ read_verilog latches.v +design -save read proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check - -design -load preopt synth_xilinx -cd top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read + +synth_xilinx +#cd top + select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 -select -assert-count 3 t:LDCE -select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D +select -assert-count 3 t:$_DLATCH_P_ +#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D +#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D diff --git a/tests/xilinx/logic.v b/tests/xilinx/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/xilinx/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys new file mode 100644 index 000000000..e138ae6a3 --- /dev/null +++ b/tests/xilinx/logic.ys @@ -0,0 +1,10 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT1 +select -assert-count 6 t:LUT2 +select -assert-count 2 t:LUT4 +select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D diff --git a/tests/xilinx/memory.v b/tests/xilinx/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/xilinx/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/xilinx/memory.ys b/tests/xilinx/memory.ys new file mode 100644 index 000000000..5402513a2 --- /dev/null +++ b/tests/xilinx/memory.ys @@ -0,0 +1,17 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM64X1D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D diff --git a/tests/xilinx/mul.v b/tests/xilinx/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/xilinx/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys new file mode 100644 index 000000000..ec30c9c2c --- /dev/null +++ b/tests/xilinx/mul.ys @@ -0,0 +1,15 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 12 t:LUT2 +select -assert-count 1 t:LUT3 +select -assert-count 6 t:LUT4 +select -assert-count 1 t:LUT5 +select -assert-count 33 t:LUT6 +select -assert-count 11 t:MUXCY +select -assert-count 1 t:MUXF7 +select -assert-count 12 t:XORCY +select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/xilinx/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys new file mode 100644 index 000000000..6ecee58f5 --- /dev/null +++ b/tests/xilinx/mux.ys @@ -0,0 +1,10 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 2 t:LUT3 +select -assert-count 5 t:LUT6 +select -assert-none t:LUT3 t:LUT6 %% t:* %D diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh index ea56b70f0..2c72ca3a9 100755 --- a/tests/xilinx/run-test.sh +++ b/tests/xilinx/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/xilinx/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/xilinx/shifter.ys b/tests/xilinx/shifter.ys new file mode 100644 index 000000000..84e16f41e --- /dev/null +++ b/tests/xilinx/shifter.ys @@ -0,0 +1,11 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v new file mode 100644 index 000000000..3fa6eb6c6 --- /dev/null +++ b/tests/xilinx/tribuf.v @@ -0,0 +1,29 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; +`ifndef BUG + + always @(en or i) + o <= (en)? i : 1'bZ; +`else + + always @(en or i) + o <= (en)? ~i : 1'bZ; +`endif +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys new file mode 100644 index 000000000..fc7ed37ef --- /dev/null +++ b/tests/xilinx/tribuf.ys @@ -0,0 +1,11 @@ +read_verilog tribuf.v +hierarchy -top top +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D From 6331fa5b022b9e16f9392d9604a545f86dc13385 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 10 Sep 2019 08:11:56 +0300 Subject: [PATCH 095/123] Remove xilinx_ug901 tests (will be moved to yosys-tests) --- Makefile | 1 - tests/xilinx_ug901/asym_ram_sdp_read_wider.v | 74 ----------- tests/xilinx_ug901/asym_ram_sdp_read_wider.ys | 22 ---- tests/xilinx_ug901/asym_ram_sdp_write_wider.v | 75 ----------- .../xilinx_ug901/asym_ram_sdp_write_wider.ys | 31 ----- tests/xilinx_ug901/asym_ram_tdp_read_first.v | 85 ------------ tests/xilinx_ug901/asym_ram_tdp_read_first.ys | 21 --- tests/xilinx_ug901/asym_ram_tdp_write_first.v | 92 ------------- .../xilinx_ug901/asym_ram_tdp_write_first.ys | 29 ----- tests/xilinx_ug901/black_box_1.v | 19 --- tests/xilinx_ug901/black_box_1.ys | 15 --- tests/xilinx_ug901/bytewrite_ram_1b.v | 42 ------ tests/xilinx_ug901/bytewrite_ram_1b.ys | 22 ---- tests/xilinx_ug901/bytewrite_tdp_ram_nc.v | 78 ----------- tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys | 22 ---- .../bytewrite_tdp_ram_readfirst2.v | 71 ---------- .../bytewrite_tdp_ram_readfirst2.ys | 21 --- tests/xilinx_ug901/bytewrite_tdp_ram_rf.v | 61 --------- tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys | 21 --- tests/xilinx_ug901/bytewrite_tdp_ram_wf.v | 68 ---------- tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys | 23 ---- tests/xilinx_ug901/cmacc.v | 122 ------------------ tests/xilinx_ug901/cmacc.ys | 25 ---- tests/xilinx_ug901/cmult.v | 71 ---------- tests/xilinx_ug901/cmult.ys | 31 ----- .../xilinx_ug901/dynamic_shift_registers_1.v | 21 --- .../xilinx_ug901/dynamic_shift_registers_1.ys | 15 --- tests/xilinx_ug901/dynpreaddmultadd.v | 47 ------- tests/xilinx_ug901/dynpreaddmultadd.ys | 31 ----- tests/xilinx_ug901/fsm_1.v | 42 ------ tests/xilinx_ug901/fsm_1.ys | 16 --- tests/xilinx_ug901/latches.v | 17 --- tests/xilinx_ug901/latches.ys | 10 -- tests/xilinx_ug901/macc.v | 47 ------- tests/xilinx_ug901/macc.ys | 23 ---- tests/xilinx_ug901/mult_unsigned.v | 33 ----- tests/xilinx_ug901/mult_unsigned.ys | 29 ----- tests/xilinx_ug901/presubmult.v | 43 ------ tests/xilinx_ug901/presubmult.ys | 23 ---- .../xilinx_ug901/ram_simple_dual_one_clock.v | 25 ---- .../xilinx_ug901/ram_simple_dual_one_clock.ys | 20 --- .../xilinx_ug901/ram_simple_dual_two_clocks.v | 30 ----- .../ram_simple_dual_two_clocks.ys | 20 --- tests/xilinx_ug901/rams_dist.v | 24 ---- tests/xilinx_ug901/rams_dist.ys | 21 --- tests/xilinx_ug901/rams_init_file.data | 64 --------- tests/xilinx_ug901/rams_init_file.v | 24 ---- tests/xilinx_ug901/rams_init_file.ys | 22 ---- tests/xilinx_ug901/rams_pipeline.v | 42 ------ tests/xilinx_ug901/rams_pipeline.ys | 22 ---- tests/xilinx_ug901/rams_sp_nc.v | 26 ---- tests/xilinx_ug901/rams_sp_nc.ys | 22 ---- tests/xilinx_ug901/rams_sp_rf.v | 26 ---- tests/xilinx_ug901/rams_sp_rf.ys | 22 ---- tests/xilinx_ug901/rams_sp_rf_rst.v | 29 ----- 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tests/xilinx && bash run-test.sh $(SEEDOPT) - +cd tests/xilinx_ug901 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v deleted file mode 100644 index 0716dffdc..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v +++ /dev/null @@ -1,74 +0,0 @@ -// Asymmetric port RAM -// Read Wider than Write. Read Statement in loop -//asym_ram_sdp_read_wider.v - -module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); -parameter WIDTHA = 4; -parameter SIZEA = 1024; -parameter ADDRWIDTHA = 10; - -parameter WIDTHB = 16; -parameter SIZEB = 256; -parameter ADDRWIDTHB = 8; -input clkA; -input clkB; -input weA; -input enaA, enaB; -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -output [WIDTHB-1:0] doB; -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHB-1:0] readB; - -always @(posedge clkA) -begin - if (enaA) begin - if (weA) - RAM[addrA] <= diA; - end -end - - -always @(posedge clkB) -begin : ramread - integer i; - reg [log2RATIO-1:0] lsbaddr; - if (enaB) begin - for (i = 0; i < RATIO; i = i+1) begin - lsbaddr = i; - readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; - end - end -end -assign doB = readB; - -endmodule - diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys deleted file mode 100644 index c63157cdf..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog asym_ram_sdp_read_wider.v -hierarchy -top asym_ram_sdp_read_wider -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_sdp_read_wider -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 1 t:LUT2 -select -assert-count 4 t:RAMB18E1 - -select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v deleted file mode 100644 index 22d12d2ce..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v +++ /dev/null @@ -1,75 +0,0 @@ -// Asymmetric port RAM -// Write wider than Read. Write Statement in a loop. -// asym_ram_sdp_write_wider.v - -module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); -parameter WIDTHB = 4; -//Default parameters were changed because of slow test -//parameter SIZEB = 1024; -//parameter ADDRWIDTHB = 10; -parameter SIZEB = 256; -parameter ADDRWIDTHB = 8; - -//parameter WIDTHA = 16; -parameter WIDTHA = 8; -parameter SIZEA = 256; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA; -input enaA, enaB; -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -output [WIDTHB-1:0] doB; -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) begin - if (enaB) begin - readB <= RAM[addrB]; - end -end -assign doB = readB; - -always @(posedge clkA) -begin : ramwrite - integer i; - reg [log2RATIO-1:0] lsbaddr; - for (i=0; i< RATIO; i= i+ 1) begin : write1 - lsbaddr = i; - if (enaA) begin - if (weA) - RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; - end - end -end - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys deleted file mode 100644 index 229d98df6..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys +++ /dev/null @@ -1,31 +0,0 @@ -read_verilog asym_ram_sdp_write_wider.v -hierarchy -top asym_ram_sdp_write_wider -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_sdp_write_wider -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 1028 t:FDRE -select -assert-count 170 t:LUT2 -select -assert-count 6 t:LUT3 -select -assert-count 518 t:LUT4 -select -assert-count 10 t:LUT5 -select -assert-count 484 t:LUT6 -select -assert-count 157 t:MUXF7 -select -assert-count 3 t:MUXF8 - -#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4 -#select -assert-count 8 t:RAM128X1D - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v deleted file mode 100644 index 2b807a382..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_read_first.v +++ /dev/null @@ -1,85 +0,0 @@ -// Asymetric RAM - TDP -// READ_FIRST MODE. -// asym_ram_tdp_read_first.v - - -module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); -parameter WIDTHB = 4; -parameter SIZEB = 1024; -parameter ADDRWIDTHB = 10; -parameter WIDTHA = 16; -parameter SIZEA = 256; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA, weB; -input enaA, enaB; - -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -input [WIDTHB-1:0] diB; - -output [WIDTHA-1:0] doA; -output [WIDTHB-1:0] doB; - -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHA-1:0] readA; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) -begin - if (enaB) begin - readB <= RAM[addrB] ; - if (weB) - RAM[addrB] <= diB; - end -end - - -always @(posedge clkA) -begin : portA - integer i; - reg [log2RATIO-1:0] lsbaddr ; - for (i=0; i< RATIO; i= i+ 1) begin - lsbaddr = i; - if (enaA) begin - readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}]; - - if (weA) - RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; - end - end -end - -assign doA = readA; -assign doB = readB; - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys deleted file mode 100644 index 5f96b800c..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog asym_ram_tdp_read_first.v -hierarchy -top asym_ram_tdp_read_first -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_tdp_read_first -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 1 t:$mem -select -assert-count 2 t:LUT2 - -select -assert-none t:$mem t:LUT2 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v deleted file mode 100644 index 90187ea26..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_write_first.v +++ /dev/null @@ -1,92 +0,0 @@ -// Asymmetric port RAM - TDP -// WRITE_FIRST MODE. -// asym_ram_tdp_write_first.v - - -module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); -parameter WIDTHB = 4; -//Default parameters were changed because of slow test -//parameter SIZEB = 1024; -//parameter ADDRWIDTHB = 10; -parameter SIZEB = 32; -parameter ADDRWIDTHB = 8; - -//parameter WIDTHA = 16; -parameter WIDTHA = 4; -//parameter SIZEA = 256; -parameter SIZEA = 32; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA, weB; -input enaA, enaB; - -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -input [WIDTHB-1:0] diB; - -output [WIDTHA-1:0] doA; -output [WIDTHB-1:0] doB; - -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHA-1:0] readA; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) -begin - if (enaB) begin - if (weB) - RAM[addrB] = diB; - readB = RAM[addrB] ; - end -end - - -always @(posedge clkA) -begin : portA - integer i; - reg [log2RATIO-1:0] lsbaddr ; - for (i=0; i< RATIO; i= i+ 1) begin - lsbaddr = i; - if (enaA) begin - - if (weA) - RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH]; - - readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}]; - end - end -end - -assign doA = readA; -assign doB = readB; - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys deleted file mode 100644 index bbe3cc849..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys +++ /dev/null @@ -1,29 +0,0 @@ -read_verilog asym_ram_tdp_write_first.v -hierarchy -top asym_ram_tdp_write_first -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_tdp_write_first -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 200 t:FDRE -select -assert-count 10 t:LUT2 -select -assert-count 44 t:LUT3 -select -assert-count 81 t:LUT4 -select -assert-count 104 t:LUT5 -select -assert-count 560 t:LUT6 -select -assert-count 261 t:MUXF7 -select -assert-count 127 t:MUXF8 - - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v deleted file mode 100644 index 40caa1b10..000000000 --- a/tests/xilinx_ug901/black_box_1.v +++ /dev/null @@ -1,19 +0,0 @@ -// Black Box -// black_box_1.v -// -(* black_box *) module black_box1 (in1, in2, dout); -input in1, in2; -output dout; -endmodule - -module black_box_1 (DI_1, DI_2, DOUT); -input DI_1, DI_2; -output DOUT; - -black_box1 U1 ( - .in1(DI_1), - .in2(DI_2), - .dout(DOUT) - ); - -endmodule diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys deleted file mode 100644 index acf0b5761..000000000 --- a/tests/xilinx_ug901/black_box_1.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog black_box_1.v -hierarchy -top black_box_1 -proc -tribuf -flatten -synth -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd black_box_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 black box. -#stat -#select -assert-count 0 t:LUT1 -#select -assert-count 1 t:$_TBUF_ -#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v deleted file mode 100644 index 46d86c297..000000000 --- a/tests/xilinx_ug901/bytewrite_ram_1b.v +++ /dev/null @@ -1,42 +0,0 @@ -// Single-Port BRAM with Byte-wide Write Enable -// Read-First mode -// Single-process description -// Compact description of the write with a generate-for -// statement -// Column width and number of columns easily configurable -// -// bytewrite_ram_1b.v -// - -module bytewrite_ram_1b (clk, we, addr, di, do); - -parameter SIZE = 1024; -parameter ADDR_WIDTH = 10; -parameter COL_WIDTH = 8; -parameter NB_COL = 4; - -input clk; -input [NB_COL-1:0] we; -input [ADDR_WIDTH-1:0] addr; -input [NB_COL*COL_WIDTH-1:0] di; -output reg [NB_COL*COL_WIDTH-1:0] do; - -reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; - -always @(posedge clk) -begin - do <= RAM[addr]; -end - -generate genvar i; -for (i = 0; i < NB_COL; i = i+1) -begin -always @(posedge clk) -begin - if (we[i]) - RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; - end -end -endgenerate - -endmodule diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys deleted file mode 100644 index 4f0967801..000000000 --- a/tests/xilinx_ug901/bytewrite_ram_1b.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog bytewrite_ram_1b.v -hierarchy -top bytewrite_ram_1b -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd bytewrite_ram_1b -stat -#Vivado synthesizes 1 RAMB36E1. -select -assert-count 1 t:BUFG -select -assert-count 32 t:LUT2 -select -assert-count 8 t:RAMB36E1 - -select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v deleted file mode 100644 index 1093b0838..000000000 --- a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v +++ /dev/null @@ -1,78 +0,0 @@ -// -// True-Dual-Port BRAM with Byte-wide Write Enable -// No-Change mode -// -// bytewrite_tdp_ram_nc.v -// -// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended -module bytewrite_tdp_ram_nc - #( - //--------------------------------------------------------------- - parameter NUM_COL = 4, - parameter COL_WIDTH = 8, - parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth - parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits - //--------------------------------------------------------------- - ) ( - input clkA, - input enaA, - input [NUM_COL-1:0] weA, - input [ADDR_WIDTH-1:0] addrA, - input [DATA_WIDTH-1:0] dinA, - output reg [DATA_WIDTH-1:0] doutA, - - input clkB, - input enaB, - input [NUM_COL-1:0] weB, - input [ADDR_WIDTH-1:0] addrB, - input [DATA_WIDTH-1:0] dinB, - output reg [DATA_WIDTH-1:0] doutB - ); - - - // Core Memory - reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; - - // Port-A Operation - generate - genvar i; - for(i=0;i run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v deleted file mode 100644 index a8b144bcd..000000000 --- a/tests/xilinx_ug901/sfir_shifter.v +++ /dev/null @@ -1,19 +0,0 @@ -//sfir_shifter.v -(* dont_touch = "yes" *) -module sfir_shifter #(parameter dsize = 16, nbtap = 4) - (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout); - - (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1]; - integer i; - - always @(posedge clk) - begin - tmp[0] <= datain; - for (i=0; i<=2*nbtap-2; i=i+1) - tmp[i+1] <= tmp[i]; - end - - assign dataout = tmp[2*nbtap-1]; - -endmodule -// sfir_shifter diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys deleted file mode 100644 index b9fbeb8cb..000000000 --- a/tests/xilinx_ug901/sfir_shifter.ys +++ /dev/null @@ -1,16 +0,0 @@ -read_verilog sfir_shifter.v -hierarchy -top sfir_shifter -proc -flatten -#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd sfir_shifter -#Vivado synthesizes 32 FDRE, 16 SRL16E. -stat -select -assert-count 1 t:BUFG -select -assert-count 16 t:SRL16E - -select -assert-none t:BUFG t:SRL16E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v deleted file mode 100644 index 77a3ec893..000000000 --- a/tests/xilinx_ug901/shift_registers_0.v +++ /dev/null @@ -1,22 +0,0 @@ -// 8-bit Shift Register -// Rising edge clock -// Active high clock enable -// Concatenation-based template -// File: shift_registers_0.v - -module shift_registers_0 (clk, clken, SI, SO); -parameter WIDTH = 32; -input clk, clken, SI; -output SO; - -reg [WIDTH-1:0] shreg; - -always @(posedge clk) - begin - if (clken) - shreg = {shreg[WIDTH-2:0], SI}; - end - -assign SO = shreg[WIDTH-1]; - -endmodule diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys deleted file mode 100644 index 89da1d7cc..000000000 --- a/tests/xilinx_ug901/shift_registers_0.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog shift_registers_0.v -hierarchy -top shift_registers_0 -proc -flatten -#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check - -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd shift_registers_0 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. -select -assert-count 1 t:BUFG -select -assert-count 1 t:SRLC32E -select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v deleted file mode 100644 index d50820e7b..000000000 --- a/tests/xilinx_ug901/shift_registers_1.v +++ /dev/null @@ -1,24 +0,0 @@ -// 32-bit Shift Register -// Rising edge clock -// Active high clock enable -// For-loop based template -// File: shift_registers_1.v - -module shift_registers_1 (clk, clken, SI, SO); -parameter WIDTH = 32; -input clk, clken, SI; -output SO; -reg [WIDTH-1:0] shreg; - -integer i; -always @(posedge clk) -begin - if (clken) - begin - for (i = 0; i < WIDTH-1; i = i+1) - shreg[i+1] <= shreg[i]; - shreg[0] <= SI; - end -end -assign SO = shreg[WIDTH-1]; -endmodule diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys deleted file mode 100644 index b53b6cb25..000000000 --- a/tests/xilinx_ug901/shift_registers_1.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog shift_registers_1.v -hierarchy -top shift_registers_1 -proc -flatten -#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check - -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd shift_registers_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. -select -assert-count 1 t:BUFG -select -assert-count 1 t:SRLC32E -select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v deleted file mode 100644 index 6535b24c4..000000000 --- a/tests/xilinx_ug901/squarediffmacc.v +++ /dev/null @@ -1,52 +0,0 @@ -// This module performs subtraction of two inputs, squaring on the diff -// and then accumulation -// This can be implemented in 1 DSP Block (Ultrascale architecture) -// File : squarediffmacc.v -module squarediffmacc # ( - //Default parameters were changed because of slow test - //parameter SIZEIN = 16, - //SIZEOUT = 40 - parameter SIZEIN = 8, - SIZEOUT = 20 - ) - ( - input clk, - input ce, - input sload, - input signed [SIZEIN-1:0] a, - input signed [SIZEIN-1:0] b, - output signed [SIZEOUT+1:0] accum_out - ); - -// Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; -reg signed [SIZEIN:0] diff_reg; -reg sload_reg; -reg signed [2*SIZEIN+1:0] m_reg; -reg signed [SIZEOUT-1:0] adder_out, old_result; - - always @(sload_reg or adder_out) - if (sload_reg) - old_result <= 0; - else - // 'sload' is now and opens the accumulation loop. - // The accumulator takes the next multiplier output - // in the same cycle. - old_result <= adder_out; - - always @(posedge clk) - if (ce) - begin - a_reg <= a; - b_reg <= b; - diff_reg <= a_reg - b_reg; - m_reg <= diff_reg * diff_reg; - sload_reg <= sload; - // Store accumulation result into a register - adder_out <= old_result + m_reg; - end - - // Output accumulation result - assign accum_out = adder_out; - -endmodule // squarediffmacc diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys deleted file mode 100644 index 92474bea3..000000000 --- a/tests/xilinx_ug901/squarediffmacc.ys +++ /dev/null @@ -1,23 +0,0 @@ -read_verilog squarediffmacc.v -hierarchy -top squarediffmacc -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd squarediffmacc -#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT. -stat -select -assert-count 1 t:BUFG -select -assert-count 64 t:FDRE -select -assert-count 78 t:LUT2 -select -assert-count 7 t:LUT3 -select -assert-count 11 t:LUT4 -select -assert-count 8 t:LUT5 -select -assert-count 125 t:LUT6 -select -assert-count 44 t:MUXCY -select -assert-count 50 t:MUXF7 -select -assert-count 17 t:MUXF8 -select -assert-count 47 t:XORCY - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v deleted file mode 100644 index 0f41b67bc..000000000 --- a/tests/xilinx_ug901/squarediffmult.v +++ /dev/null @@ -1,42 +0,0 @@ -// Squarer support for DSP block (DSP48E2) with -// pre-adder configured -// as subtractor -// File: squarediffmult.v - -module squarediffmult # (parameter SIZEIN = 16) - ( - input clk, ce, rst, - input signed [SIZEIN-1:0] a, b, - output signed [2*SIZEIN+1:0] square_out - ); - - // Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; -reg signed [SIZEIN:0] diff_reg; -reg signed [2*SIZEIN+1:0] m_reg, p_reg; - -always @(posedge clk) -begin - if (rst) - begin - a_reg <= 0; - b_reg <= 0; - diff_reg <= 0; - m_reg <= 0; - p_reg <= 0; - end - else - if (ce) - begin - a_reg <= a; - b_reg <= b; - diff_reg <= a_reg - b_reg; - m_reg <= diff_reg * diff_reg; - p_reg <= m_reg; - end -end - -// Output result -assign square_out = p_reg; - -endmodule // squarediffmult diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys deleted file mode 100644 index 3468e5bb4..000000000 --- a/tests/xilinx_ug901/squarediffmult.ys +++ /dev/null @@ -1,30 +0,0 @@ -read_verilog squarediffmult.v -hierarchy -top squarediffmult -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd squarediffmult -stat -#Vivado synthesizes 16 FDRE, 1 DSP48E1. -select -assert-count 1 t:BUFG -select -assert-count 117 t:FDRE -select -assert-count 223 t:LUT2 -select -assert-count 50 t:LUT3 -select -assert-count 38 t:LUT4 -select -assert-count 56 t:LUT5 -select -assert-count 372 t:LUT6 -select -assert-count 49 t:MUXCY -select -assert-count 99 t:MUXF7 -select -assert-count 26 t:MUXF8 -select -assert-count 51 t:XORCY - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v deleted file mode 100644 index c23c7491c..000000000 --- a/tests/xilinx_ug901/top_mux.v +++ /dev/null @@ -1,18 +0,0 @@ -// Multiplexer using case statement -module mux4 (sel, a, b, c, d, outmux); -input [1:0] sel; -input [1:0] a, b, c, d; -output [1:0] outmux; -reg [1:0] outmux; - -always @ * - begin - case(sel) - 2'b00 : outmux = a; - 2'b01 : outmux = b; - 2'b10 : outmux = c; - 2'b11 : outmux = d; - endcase - end -endmodule - diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys deleted file mode 100644 index 0245f3bbc..000000000 --- a/tests/xilinx_ug901/top_mux.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog top_mux.v -hierarchy -top mux4 -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd mux4 -#Vivado synthesizes 2 LUT. -stat -select -assert-count 2 t:LUT6 - -select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v deleted file mode 100644 index 0038a9989..000000000 --- a/tests/xilinx_ug901/tristates_1.v +++ /dev/null @@ -1,17 +0,0 @@ -// Tristate Description Using Combinatorial Always Block -// File: tristates_1.v -// -module tristates_1 (T, I, O); -input T, I; -output O; -reg O; - -always @(T or I) -begin - if (~T) - O = I; - else - O = 1'bZ; -end - -endmodule diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys deleted file mode 100644 index 7c13dc227..000000000 --- a/tests/xilinx_ug901/tristates_1.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog tristates_1.v -hierarchy -top tristates_1 -proc -tribuf -flatten -synth -equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristates_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 3 IBUF, 1 OBUFT. -select -assert-count 1 t:LUT1 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v deleted file mode 100644 index 0c70a1257..000000000 --- a/tests/xilinx_ug901/tristates_2.v +++ /dev/null @@ -1,10 +0,0 @@ -// Tristate Description Using Concurrent Assignment -// File: tristates_2.v -// -module tristates_2 (T, I, O); -input T, I; -output O; - -assign O = (~T) ? I: 1'bZ; - -endmodule diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys deleted file mode 100644 index ba2e1d855..000000000 --- a/tests/xilinx_ug901/tristates_2.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog tristates_2.v -hierarchy -top tristates_2 -proc -tribuf -flatten -synth -equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristates_2 # Constrain all select calls below inside the top module -#Vivado synthesizes 3 IBUF, 1 OBUFT. -select -assert-count 1 t:LUT1 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v deleted file mode 100644 index f5e843dc9..000000000 --- a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v +++ /dev/null @@ -1,78 +0,0 @@ -// Xilinx UltraRAM Single Port No Change Mode. This code implements -// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is -// when data is written, the output of RAM is unchanged. Only when write is -// inactive data corresponding to the address is presented on the output port. -// -module xilinx_ultraram_single_port_no_change #( -//Default parameters were changed because of slow test - //parameter AWIDTH = 12, // Address Width - //parameter DWIDTH = 72, // Data Width - //parameter NBPIPE = 3 // Number of pipeline Registers - parameter AWIDTH = 8, // Address Width - parameter DWIDTH = 8, // Data Width - parameter NBPIPE = 3 // Number of pipeline Registers - ) ( - input clk, // Clock - input rst, // Reset - input we, // Write Enable - input regce, // Output Register Enable - input mem_en, // Memory Enable - input [DWIDTH-1:0] din, // Data Input - input [AWIDTH-1:0] addr, // Address Input - output reg [DWIDTH-1:0] dout // Data Output - ); - -(* ram_style = "ultra" *) -reg [DWIDTH-1:0] mem[(1< Date: Tue, 10 Sep 2019 08:36:59 +0300 Subject: [PATCH 096/123] Fix latches.ys test --- tests/xilinx/latches.ys | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 9ab562bcf..042ee2d4f 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -11,10 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p design -load read synth_xilinx -#cd top - +flatten +cd top select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 select -assert-count 3 t:$_DLATCH_P_ -#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D -#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D +select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D From 7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 11 Sep 2019 17:01:19 +0300 Subject: [PATCH 097/123] Add comment with expected behavior for latches,tribuf tests;Update adffs test --- tests/xilinx/adffs.v | 18 +++++++----------- tests/xilinx/adffs.ys | 5 ++--- tests/xilinx/latches.ys | 1 + tests/xilinx/tribuf.ys | 1 + 4 files changed, 11 insertions(+), 14 deletions(-) diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/xilinx/adffs.v +++ b/tests/xilinx/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 96d8e176f..38c82a36f 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -9,6 +9,5 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 3 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 4 t:LUT2 -select -assert-count 4 t:LUT3 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D +select -assert-count 5 t:LUT2 +select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 042ee2d4f..1f643cb4e 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -15,5 +15,6 @@ flatten cd top select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 +#Xilinx Vivado synthesizes LDCE cell for this case. Need support it. select -assert-count 3 t:$_DLATCH_P_ select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index fc7ed37ef..76b00647d 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,5 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D From df7fe40529f7e0a26626ac1b0ed12acf66bb40d3 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Wed, 11 Sep 2019 20:34:22 +0300 Subject: [PATCH 098/123] Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index cc00b1a27..52e536a7f 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 -select -assert-count 21 t:LUT2 +select -assert-count 23 t:LUT2 select -assert-count 13 t:LUT4 select -assert-count 6 t:LUT5 select -assert-count 80 t:LUT6 From 205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Wed, 11 Sep 2019 21:28:40 +0300 Subject: [PATCH 099/123] Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 52e536a7f..e1c4d6912 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -7,7 +7,7 @@ cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 -select -assert-count 13 t:LUT4 +select -assert-count 12 t:LUT4 select -assert-count 6 t:LUT5 select -assert-count 80 t:LUT6 select -assert-count 65 t:MUXCY From c340d54657688542c5f3a8dabe3f68563dcc8d1c Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 06:24:18 +0300 Subject: [PATCH 100/123] Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index e1c4d6912..7db336d00 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 select -assert-count 12 t:LUT4 -select -assert-count 6 t:LUT5 +select -assert-count 9 t:LUT5 select -assert-count 80 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 36 t:MUXF7 From df6d0b95da89a4a7bd558dab0c112f5c7a989561 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 07:13:49 +0300 Subject: [PATCH 101/123] Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 7db336d00..c5855f1dd 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -9,7 +9,7 @@ select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 select -assert-count 12 t:LUT4 select -assert-count 9 t:LUT5 -select -assert-count 80 t:LUT6 +select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 36 t:MUXF7 select -assert-count 9 t:MUXF8 From 68f9239c5758e4f48dc290871cf108f85d5f5387 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 13:58:49 +0300 Subject: [PATCH 102/123] Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index c5855f1dd..6a4c1e971 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -11,7 +11,7 @@ select -assert-count 12 t:LUT4 select -assert-count 9 t:LUT5 select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY -select -assert-count 36 t:MUXF7 +select -assert-count 39 t:MUXF7 select -assert-count 9 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D From bb70eb977dc29dbfe8cfb9af847046f387bd54b2 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 14:54:01 +0300 Subject: [PATCH 103/123] Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 6a4c1e971..4518db8bf 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -12,6 +12,6 @@ select -assert-count 9 t:LUT5 select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 39 t:MUXF7 -select -assert-count 9 t:MUXF8 +select -assert-count 15 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D From 305672170bcd6346bebbb01c843225fe0392a37d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 17 Sep 2019 11:53:49 +0300 Subject: [PATCH 104/123] adffs test update (equiv_opt -multiclock) --- tests/xilinx/adffs.ys | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 38c82a36f..961e08ae9 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,13 +1,14 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 3 t:FDRE +select -assert-count 2 t:FDCE +select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 5 t:LUT2 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D +select -assert-count 1 t:LUT1 +select -assert-count 2 t:LUT2 +select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D From eded90b6b42117ba427469a6100c74e708c4f142 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:16:45 -0700 Subject: [PATCH 105/123] Move $x to end as 7f0eec8 --- tests/xilinx/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/xilinx/run-test.sh +++ b/tests/xilinx/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then From a12801843bb400bba8f2f8ce99a3f524ac05b7e8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:17:59 -0700 Subject: [PATCH 106/123] Add comment for lack of tristate logic pointing to #1225 --- tests/xilinx/tribuf.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 76b00647d..696be2620 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,6 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. +# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D From 08bd1816e39d2abfbe36ce0b58c0d4506db303e4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:20:47 -0700 Subject: [PATCH 107/123] Update area for div_mod --- tests/xilinx/div_mod.ys | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 4518db8bf..da7e60a9a 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -6,12 +6,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 -select -assert-count 23 t:LUT2 -select -assert-count 12 t:LUT4 -select -assert-count 9 t:LUT5 -select -assert-count 84 t:LUT6 +select -assert-count 19 t:LUT2 +select -assert-count 13 t:LUT4 +select -assert-count 6 t:LUT5 +select -assert-count 82 t:LUT6 select -assert-count 65 t:MUXCY -select -assert-count 39 t:MUXF7 -select -assert-count 15 t:MUXF8 +select -assert-count 37 t:MUXF7 +select -assert-count 11 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D From 5b7bc3ab85d31920883995636d26dc5b971ca24d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:38:06 -0700 Subject: [PATCH 108/123] Update mul test to DSP48E1 --- tests/xilinx/mul.ys | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys index ec30c9c2c..f5306e848 100644 --- a/tests/xilinx/mul.ys +++ b/tests/xilinx/mul.ys @@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 12 t:LUT2 -select -assert-count 1 t:LUT3 -select -assert-count 6 t:LUT4 -select -assert-count 1 t:LUT5 -select -assert-count 33 t:LUT6 -select -assert-count 11 t:MUXCY -select -assert-count 1 t:MUXF7 -select -assert-count 12 t:XORCY -select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D +select -assert-count 1 t:DSP48E1 +select -assert-none t:DSP48E1 %% t:* %D From 8422ad3e3a5db583f59906f8a5d81587dd777f6d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:56:19 -0700 Subject: [PATCH 109/123] Use built-in async2sync call as per #1417 --- tests/xilinx/latches.ys | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 1f643cb4e..795ac9074 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -4,11 +4,7 @@ design -save read proc async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_xilinx equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -design -load read synth_xilinx flatten From 3b4408432073ec4d9a2b8995b8e08a5bf6175f39 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:57:26 -0700 Subject: [PATCH 110/123] Add -assert --- tests/xilinx/counter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index b602b74d7..3bb3a8eb0 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module From a7fbc8c3fe1e2ad867ffc3456943644e70ab2575 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:19:26 +0200 Subject: [PATCH 111/123] Test per flip-flop type --- tests/xilinx/adffs.v | 40 ---------------------------------- tests/xilinx/adffs.ys | 50 ++++++++++++++++++++++++++++++++++--------- 2 files changed, 40 insertions(+), 50 deletions(-) diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v index 05e68caf7..223b52d21 100644 --- a/tests/xilinx/adffs.v +++ b/tests/xilinx/adffs.v @@ -45,43 +45,3 @@ module ndffnr else q <= d; endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 961e08ae9..7edab67c7 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,14 +1,44 @@ read_verilog adffs.v -proc -flatten -equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +design -save read +proc +hierarchy -top adff +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 2 t:FDCE -select -assert-count 1 t:FDRE -select -assert-count 1 t:FDRE_1 +select -assert-count 1 t:FDCE +select -assert-none t:BUFG t:FDCE %% t:* %D + +design -load read +proc +hierarchy -top adffn +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDCE select -assert-count 1 t:LUT1 -select -assert-count 2 t:LUT2 -select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D + +design -load read +proc +hierarchy -top dffs +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT2 +select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D + +design -load read +proc +hierarchy -top ndffnr +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE_1 +select -assert-count 1 t:LUT2 +select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D \ No newline at end of file From d37cd267a56295737e95f5bc5e6f446c27605639 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:24:37 +0200 Subject: [PATCH 112/123] Removed alu and div_mod test as agreed, ignore generated files --- tests/xilinx/.gitignore | 1 + tests/xilinx/alu.v | 19 ------------------- tests/xilinx/alu.ys | 21 --------------------- tests/xilinx/div_mod.v | 13 ------------- tests/xilinx/div_mod.ys | 17 ----------------- 5 files changed, 1 insertion(+), 70 deletions(-) delete mode 100644 tests/xilinx/alu.v delete mode 100644 tests/xilinx/alu.ys delete mode 100644 tests/xilinx/div_mod.v delete mode 100644 tests/xilinx/div_mod.ys diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore index 54733fb71..89879f209 100644 --- a/tests/xilinx/.gitignore +++ b/tests/xilinx/.gitignore @@ -2,3 +2,4 @@ /*.out /run-test.mk /*_uut.v +/test_macc \ No newline at end of file diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/xilinx/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys deleted file mode 100644 index f85f03928..000000000 --- a/tests/xilinx/alu.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - - -select -assert-count 1 t:BUFG -select -assert-count 32 t:LUT1 -select -assert-count 142 t:LUT2 -select -assert-count 55 t:LUT3 -select -assert-count 70 t:LUT4 -select -assert-count 46 t:LUT5 -select -assert-count 625 t:LUT6 -select -assert-count 62 t:MUXCY -select -assert-count 265 t:MUXF7 -select -assert-count 79 t:MUXF8 -select -assert-count 64 t:XORCY -select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/xilinx/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys deleted file mode 100644 index da7e60a9a..000000000 --- a/tests/xilinx/div_mod.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 12 t:LUT1 -select -assert-count 19 t:LUT2 -select -assert-count 13 t:LUT4 -select -assert-count 6 t:LUT5 -select -assert-count 82 t:LUT6 -select -assert-count 65 t:MUXCY -select -assert-count 37 t:MUXF7 -select -assert-count 11 t:MUXF8 -select -assert-count 28 t:XORCY -select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D From 53bc499a907cc3bfbeb91866d8839286ae0dfdf1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:27:49 +0200 Subject: [PATCH 113/123] Clean verilog code from not used define block --- tests/xilinx/shifter.v | 6 ------ tests/xilinx/tribuf.v | 6 ------ 2 files changed, 12 deletions(-) diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v index c55632552..04ae49d83 100644 --- a/tests/xilinx/shifter.v +++ b/tests/xilinx/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v index 3fa6eb6c6..75149d8ba 100644 --- a/tests/xilinx/tribuf.v +++ b/tests/xilinx/tribuf.v @@ -2,15 +2,9 @@ module tristate (en, i, o); input en; input i; output reg o; -`ifndef BUG always @(en or i) o <= (en)? i : 1'bZ; -`else - - always @(en or i) - o <= (en)? ~i : 1'bZ; -`endif endmodule From fba6229718a45188514e016eec8678f1facb82a4 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:19:17 +0200 Subject: [PATCH 114/123] Fix formatting --- tests/xilinx/adffs.ys | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 7edab67c7..2d23749ac 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -8,8 +8,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE + select -assert-none t:BUFG t:FDCE %% t:* %D + design -load read proc hierarchy -top adffn @@ -19,8 +21,10 @@ cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE select -assert-count 1 t:LUT1 + select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D + design -load read proc hierarchy -top dffs @@ -30,8 +34,10 @@ cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 + select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D + design -load read proc hierarchy -top ndffnr @@ -41,4 +47,5 @@ cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 select -assert-count 1 t:LUT2 -select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D \ No newline at end of file + +select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D From 487b38b124cbb388bd680cb54cb43c58829ca1d3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:24:22 +0200 Subject: [PATCH 115/123] Split latches into separete tests --- tests/xilinx/latches.v | 34 ---------------------------------- tests/xilinx/latches.ys | 35 +++++++++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 42 deletions(-) diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/xilinx/latches.v +++ b/tests/xilinx/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 795ac9074..68ca42b10 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -2,15 +2,34 @@ read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE -synth_xilinx -flatten -cd top +select -assert-none t:LDCE %% t:* %D + + +design -load read +proc +hierarchy -top latchn +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE select -assert-count 1 t:LUT1 + +select -assert-none t:LDCE t:LUT1 %% t:* %D + + +design -load read +proc +hierarchy -top latchsr +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE select -assert-count 2 t:LUT3 -#Xilinx Vivado synthesizes LDCE cell for this case. Need support it. -select -assert-count 3 t:$_DLATCH_P_ -select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D + +select -assert-none t:LDCE t:LUT3 %% t:* %D From 36af10280136f0fda7b743075ac52e48576abf26 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:28:18 +0200 Subject: [PATCH 116/123] Test dffs separetely --- tests/xilinx/dffs.v | 22 ---------------------- tests/xilinx/dffs.ys | 23 +++++++++++++++++++---- 2 files changed, 19 insertions(+), 26 deletions(-) diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v index d97840c43..3418787c9 100644 --- a/tests/xilinx/dffs.v +++ b/tests/xilinx/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys index 6a98994c0..2d48a816c 100644 --- a/tests/xilinx/dffs.ys +++ b/tests/xilinx/dffs.ys @@ -1,10 +1,25 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 2 t:FDRE +select -assert-count 1 t:FDRE + select -assert-none t:BUFG t:FDRE %% t:* %D + + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE + +select -assert-none t:BUFG t:FDRE %% t:* %D + From a198bcdd4ffe6b09787ea5bf2e69528ace375020 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:39:22 +0200 Subject: [PATCH 117/123] split muxes synth per type --- tests/xilinx/mux.v | 35 ----------------------------------- tests/xilinx/mux.ys | 43 +++++++++++++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v index 0814b733e..27bc0bf0b 100644 --- a/tests/xilinx/mux.v +++ b/tests/xilinx/mux.v @@ -63,38 +63,3 @@ module mux16 (D, S, Y); assign Y = D[S]; endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys index 6ecee58f5..4cdb12e47 100644 --- a/tests/xilinx/mux.ys +++ b/tests/xilinx/mux.ys @@ -1,10 +1,45 @@ read_verilog mux.v +design -save read + proc -flatten +hierarchy -top mux2 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 + +select -assert-none t:LUT3 %% t:* %D + + +design -load read +proc +hierarchy -top mux4 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D + + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT6 -select -assert-count 2 t:LUT3 -select -assert-count 5 t:LUT6 select -assert-none t:LUT3 t:LUT6 %% t:* %D + + +design -load read +proc +hierarchy -top mux16 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D From 1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:39:34 +0200 Subject: [PATCH 118/123] remove not needed top module --- tests/xilinx/tribuf.v | 15 --------------- tests/xilinx/tribuf.ys | 4 ++-- 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v index 75149d8ba..c64468253 100644 --- a/tests/xilinx/tribuf.v +++ b/tests/xilinx/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); always @(en or i) o <= (en)? i : 1'bZ; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 696be2620..c9cfb8546 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -1,12 +1,12 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc tribuf flatten synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D From b2f0d75807c99c74f9860098b74e8300514ba9e5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:41:45 +0200 Subject: [PATCH 119/123] remove not needed top module --- tests/xilinx/fsm.v | 18 ------------------ tests/xilinx/fsm.ys | 4 ++-- 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/xilinx/fsm.v +++ b/tests/xilinx/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys index 3b73891c2..a9e94c2c0 100644 --- a/tests/xilinx/fsm.ys +++ b/tests/xilinx/fsm.ys @@ -1,10 +1,10 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc flatten equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 5 t:FDRE From 980df499abb63e5dfadc29b3326032b55b6dbf18 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 17 Oct 2019 17:24:53 +0200 Subject: [PATCH 120/123] Make equivalence work with latest master --- tests/xilinx/adffs.ys | 8 ++++---- tests/xilinx/counter.ys | 2 +- tests/xilinx/latches.ys | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 2d23749ac..9e8ba44ab 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -3,7 +3,7 @@ design -save read proc hierarchy -top adff -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D design -load read proc hierarchy -top adffn -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -28,7 +28,7 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D design -load read proc hierarchy -top dffs -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -41,7 +41,7 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D design -load read proc hierarchy -top ndffnr -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index 3bb3a8eb0..459541656 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 68ca42b10..52e96834d 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -3,7 +3,7 @@ design -save read proc hierarchy -top latchp -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D design -load read proc hierarchy -top latchn -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -26,7 +26,7 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D design -load read proc hierarchy -top latchsr -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE From e6ad714d20134612521e995c72e4fa06ed791dd3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 08:06:57 +0200 Subject: [PATCH 121/123] hierarchy - proc reorder --- tests/xilinx/.gitignore | 2 +- tests/xilinx/add_sub.ys | 1 + tests/xilinx/adffs.ys | 8 ++++---- tests/xilinx/dffs.ys | 4 ++-- tests/xilinx/latches.ys | 6 +++--- tests/xilinx/logic.ys | 1 + tests/xilinx/macc.ys | 4 ++-- tests/xilinx/mul.ys | 1 + tests/xilinx/mul_unsigned.ys | 3 ++- tests/xilinx/mux.ys | 8 ++++---- 10 files changed, 21 insertions(+), 17 deletions(-) diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore index 89879f209..c99b79371 100644 --- a/tests/xilinx/.gitignore +++ b/tests/xilinx/.gitignore @@ -2,4 +2,4 @@ /*.out /run-test.mk /*_uut.v -/test_macc \ No newline at end of file +/test_macc diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys index 821341f20..f06e7fa01 100644 --- a/tests/xilinx/add_sub.ys +++ b/tests/xilinx/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 9e8ba44ab..1923b9802 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDCE %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -26,8 +26,8 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -39,8 +39,8 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys index 2d48a816c..f1716dabb 100644 --- a/tests/xilinx/dffs.ys +++ b/tests/xilinx/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDRE %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 52e96834d..3eb550a42 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:LDCE %% t:* %D design -load read -proc hierarchy -top latchn +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module @@ -24,8 +24,8 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D design -load read -proc hierarchy -top latchsr +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys index e138ae6a3..9ae5993aa 100644 --- a/tests/xilinx/logic.ys +++ b/tests/xilinx/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys index 417a3b21b..6e884b35a 100644 --- a/tests/xilinx/macc.ys +++ b/tests/xilinx/macc.ys @@ -1,8 +1,8 @@ read_verilog macc.v design -save read -proc hierarchy -top macc +proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter @@ -15,8 +15,8 @@ select -assert-count 1 t:DSP48E1 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D design -load read -proc hierarchy -top macc2 +proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys index f5306e848..66a06efdc 100644 --- a/tests/xilinx/mul.ys +++ b/tests/xilinx/mul.ys @@ -1,5 +1,6 @@ read_verilog mul.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 77990bd68..62495b90c 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -1,6 +1,7 @@ read_verilog mul_unsigned.v -proc hierarchy -top mul_unsigned +proc + equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys index 4cdb12e47..420dece4e 100644 --- a/tests/xilinx/mux.ys +++ b/tests/xilinx/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:LUT3 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:LUT6 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -35,8 +35,8 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module From 0d60902fd97bba4f231f8f600434b8a69562ffff Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:04:02 +0200 Subject: [PATCH 122/123] hierarchy - proc reorder --- tests/ecp5/add_sub.ys | 1 + tests/ecp5/adffs.ys | 8 ++++---- tests/ecp5/dffs.ys | 4 ++-- tests/ecp5/latches.ys | 6 +++--- tests/ecp5/logic.ys | 1 + tests/ecp5/macc.ys | 2 +- tests/ecp5/mul.ys | 1 + tests/ecp5/mux.ys | 8 ++++---- tests/ecp5/rom.ys | 1 + 9 files changed, 18 insertions(+), 14 deletions(-) diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys index 03aec6694..ee72d732f 100644 --- a/tests/ecp5/add_sub.ys +++ b/tests/ecp5/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index 658f302d0..b129419d3 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -20,8 +20,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -30,8 +30,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 93b8595ad..a4f45d2fb 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index f32998232..fc15a6910 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -2,8 +2,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchp # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchn # Constrain all select calls below inside the top module @@ -24,8 +24,8 @@ select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys index 34125fea9..4f113a130 100644 --- a/tests/ecp5/logic.ys +++ b/tests/ecp5/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index f60281a54..1863ea4d2 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,6 +1,6 @@ read_verilog macc.v -proc hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys index 132340664..0a91f892e 100644 --- a/tests/ecp5/mul.ys +++ b/tests/ecp5/mul.ys @@ -1,5 +1,6 @@ read_verilog mul.v hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys index eada276ba..8cfbd541b 100644 --- a/tests/ecp5/mux.ys +++ b/tests/ecp5/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -22,8 +22,8 @@ select -assert-count 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -34,8 +34,8 @@ select -assert-count 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys index 8a52749a1..98645ae43 100644 --- a/tests/ecp5/rom.ys +++ b/tests/ecp5/rom.ys @@ -1,4 +1,5 @@ read_verilog rom.v +hierarchy -top top proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check From 46af9a0ff7727c2d47b1dc12501e3328cba1f2e9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:06:43 +0200 Subject: [PATCH 123/123] hierarchy - proc reorder --- tests/anlogic/add_sub.ys | 1 + tests/anlogic/dffs.ys | 4 ++-- tests/anlogic/latches.ys | 6 +++--- tests/anlogic/mux.ys | 8 ++++---- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys index 994cd0d03..b8b67cc46 100644 --- a/tests/anlogic/add_sub.ys +++ b/tests/anlogic/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys index 38dffa326..9cbe5fce7 100644 --- a/tests/anlogic/dffs.ys +++ b/tests/anlogic/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:AL_MAP_SEQ select -assert-none t:AL_MAP_SEQ %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys index ae9e15ff8..c00c7a25d 100644 --- a/tests/anlogic/latches.ys +++ b/tests/anlogic/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchn # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys index 354fc836c..64ed2a2bd 100644 --- a/tests/anlogic/mux.ys +++ b/tests/anlogic/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -11,8 +11,8 @@ select -assert-count 1 t:AL_MAP_LUT3 select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -21,8 +21,8 @@ select -assert-count 1 t:AL_MAP_LUT6 select -assert-none t:AL_MAP_LUT6 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -32,8 +32,8 @@ select -assert-count 1 t:AL_MAP_LUT6 select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module