Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff

tests/simple_abc9/abc9.v

@@ -268,23 +268,23 @@ assign o = { 1'b1, 1'bx };
 assign p = { 1'b1, 1'bx, 1'b0 };
 endmodule
 
-module abc9_test029(input clk, d, r, output reg q);
+module abc9_test029(input clk1, clk2, d, output reg q1, q2);
+always @(posedge clk1) q1 <= d;
+always @(negedge clk2) q2 <= q1;
+endmodule
+
+module abc9_test030(input clk, d, r, output reg q);
 always @(posedge clk or posedge r)
     if (r) q <= 1'b0;
     else q <= d;
 endmodule
 
-module abc9_test030(input clk, d, r, output reg q);
+module abc9_test031(input clk, d, r, output reg q);
 always @(negedge clk or posedge r)
     if (r) q <= 1'b1;
     else q <= d;
 endmodule
 
-module abc9_test032(input clk1, clk2, d, output reg q1, q2);
-always @(posedge clk1) q1 <= d;
-always @(negedge clk2) q2 <= q1;
-endmodule
-
 module abc9_test033(input clk, d, output reg q1, q2);
 always @(posedge clk) q1 <= d;
 always @(posedge clk) q2 <= q1;

tests/various/abc9.v

@@ -10,9 +10,9 @@ unknown u(~i, w);
 unknown2 u2(w, o);
 endmodule
 
-module abc9_test031(input clk, d, r, output reg q);
+module abc9_test032(input clk, d, r, output reg q);
 initial q = 1'b0;
 always @(negedge clk or negedge r)
-    if (r) q <= 1'b0;
+    if (!r) q <= 1'b0;
     else q <= d;
 endmodule

tests/various/abc9.ys

@@ -24,9 +24,9 @@ select -assert-count 1 t:unknown
 select -assert-none t:$lut t:unknown %% t: %D
 
 design -load read
-hierarchy -top abc9_test031
+hierarchy -top abc9_test032
 proc
-async2sync
+clk2fflogic
 design -save gold
 
 abc9 -lut 4