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Be more precise when connecting during ABC9 re-integration

This commit is contained in:
Eddie Hung 2019-06-12 16:04:33 -07:00
parent 8374eb1cb4
commit b3faf0246d
1 changed files with 3 additions and 1 deletions
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4
passes/techmap/abc9.cc
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@ -569,7 +569,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit(); RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
if (!a_bit.wire) { if (!a_bit.wire) {
c->setPort("\\Y", module->addWire(NEW_ID)); c->setPort("\\Y", module->addWire(NEW_ID));
module->connect(module->wires_[remap_name(y_bit.wire->name)], RTLIL::S1); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
} }
else if (!lut_costs.empty() || !lut_file.empty()) { else if (!lut_costs.empty() || !lut_file.empty()) {
RTLIL::Cell* driving_lut = nullptr; RTLIL::Cell* driving_lut = nullptr;