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Revert "Recognise default entry in case even if all cases covered (fix for #931)"

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Eddie Hung 2019-04-15 17:52:45 -07:00 committed by GitHub
parent 18a4045858
commit b3378745fd
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2 changed files with 3 additions and 4 deletions
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2
passes/proc/proc_rmdead.cc
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@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
for (size_t i = 0; i < sw->cases.size(); i++) for (size_t i = 0; i < sw->cases.size(); i++)
{ {
bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0);
for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
RTLIL::SigSpec sig = sw->cases[i]->compare[j]; RTLIL::SigSpec sig = sw->cases[i]->compare[j];

5
tests/various/muxcover.ys
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@ -8,13 +8,12 @@ read_verilog -formal <<EOT
3'b?1?: Y = B; 3'b?1?: Y = B;
3'b1??: Y = C; 3'b1??: Y = C;
3'b000: Y = D; 3'b000: Y = D;
default: Y = 'bx;
endcase endcase
endmodule endmodule
EOT EOT
## Example usage for "pmuxtree" and "muxcover" ## Examle usage for "pmuxtree" and "muxcover"
proc proc
pmuxtree pmuxtree
@ -36,7 +35,7 @@ read_verilog -formal <<EOT
3'b010: Y = B; 3'b010: Y = B;
3'b100: Y = C; 3'b100: Y = C;
3'b000: Y = D; 3'b000: Y = D;
default: Y = 'bx; default: Y = 'bx;
endcase endcase
endmodule endmodule
EOT EOT