mirror of https://github.com/YosysHQ/yosys.git
abstract: improve -init logging
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690612475d
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b3075431dc
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@ -171,23 +171,14 @@ unsigned int abstract_init(Module* mod) {
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unsigned int changed = 0;
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FfInitVals initvals;
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SigMap sigmap(mod);
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dict<SigBit, std::vector<SelReason>> selected_reps = gather_selected_reps(mod, sigmap);
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initvals.set(&sigmap, mod);
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for (auto wire : mod->selected_wires())
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for (auto bit : SigSpec(wire)) {
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// TODO these don't seem too informative
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log_debug("Removing init bit on %s due to selected wire %s\n", log_signal(bit), wire->name.c_str());
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initvals.remove_init(bit);
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changed++;
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}
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for (auto cell : mod->selected_cells())
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for (auto conn : cell->connections())
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if (cell->output(conn.first))
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for (auto bit : conn.second.bits()) {
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log_debug("Removing init bit on %s due to selected cell %s\n", log_signal(bit), cell->name.c_str());
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initvals.remove_init(bit);
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changed++;
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}
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for (auto bit : selected_reps) {
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log_debug("Removing init bit on %s due to selections:\n", log_signal(bit.first));
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explain_selections(bit.second);
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initvals.remove_init(bit.first);
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changed++;
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}
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return changed;
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}
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