riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

ecp5: ECP5 synthesis fixes 

Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-16 14:33:13 +02:00
parent 459d367913
commit b2c62ff8ef
3 changed files with 32 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/ecp5/arith_map.v
View File

@ -42,7 +42,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
function integer round_up2; function integer round_up2;
input integer N; input integer N;
begin begin
round_up2 = ((N / 2) + 1) * 2; round_up2 = ((N + 1) / 2) * 2;
end end
endfunction endfunction
@ -69,7 +69,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
); );
assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
if (i < Y_WIDTH) begin if (i+1 < Y_WIDTH) begin
assign CO[i+1] = FCO[i]; assign CO[i+1] = FCO[i];
assign Y[i+1] = Y1[i]; assign Y[i+1] = Y1[i];
end end

39
techlibs/ecp5/cells_sim.v
View File

@ -67,10 +67,15 @@ module TRELLIS_RAM16X2 (
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
wire muxwre = (WREMUX == "1") ? 1'b1 : reg muxwre;
(WREMUX == "0") ? 1'b0 : always @(*)
(WREMUX == "INV") ? ~WRE : case (WREMUX)
WRE; "1": muxwre = 1'b1;
"0": muxwre = 1'b0;
"INV": muxwre = ~WRE;
default: muxwre = WRE;
endcase
always @(posedge muxwck) always @(posedge muxwck)
if (muxwre) if (muxwre)
@ -108,10 +113,14 @@ module TRELLIS_DPR16X4 (
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
wire muxwre = (WREMUX == "1") ? 1'b1 : reg muxwre;
(WREMUX == "0") ? 1'b0 : always @(*)
(WREMUX == "INV") ? ~WRE : case (WREMUX)
WRE; "1": muxwre = 1'b1;
"0": muxwre = 1'b0;
"INV": muxwre = ~WRE;
default: muxwre = WRE;
endcase
always @(posedge muxwck) always @(posedge muxwck)
if (muxwre) if (muxwre)
@ -167,7 +176,7 @@ module DPR16X4C (
integer i; integer i;
initial begin initial begin
for (i = 0; i < 15; i = i + 1) begin for (i = 0; i < 15; i = i + 1) begin
ram[i] = conv_initval[4*i +: 4]; ram[i] <= conv_initval[4*i +: 4];
end end
end end
@ -189,10 +198,14 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
parameter SRMODE = "LSR_OVER_CE"; parameter SRMODE = "LSR_OVER_CE";
parameter REGSET = "RESET"; parameter REGSET = "RESET";
wire muxce = (CEMUX == "1") ? 1'b1 : reg muxce;
(CEMUX == "0") ? 1'b0 : always @(*)
(CEMUX == "INV") ? ~CE : case (CEMUX)
CE; "1": muxce = 1'b1;
"0": muxce = 1'b0;
"INV": muxce = ~CE;
default: muxce = CE;
endcase
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;

4
techlibs/ecp5/synth_ecp5.cc
View File

@ -172,6 +172,10 @@ struct SynthEcp5Pass : public ScriptPass
nodram = true; nodram = true;
continue; continue;
} }
if (args[argidx] == "-nomux") {
nomux = true;
continue;
}
if (args[argidx] == "-abc2") { if (args[argidx] == "-abc2") {
abc2 = true; abc2 = true;
continue; continue;