mirror of https://github.com/YosysHQ/yosys.git
Fixed segfault in AstNode::asReal
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@ -831,7 +831,7 @@ double AstNode::asReal(bool is_signed)
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{
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{
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RTLIL::Const val(bits);
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RTLIL::Const val(bits);
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bool is_negative = is_signed && val.bits.back() == RTLIL::State::S1;
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bool is_negative = is_signed && !val.bits.empty() && val.bits.back() == RTLIL::State::S1;
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if (is_negative)
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if (is_negative)
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val = const_neg(val, val, false, false, val.bits.size());
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val = const_neg(val, val, false, false, val.bits.size());
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