diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc index bc1e8ff1b..a71a1227e 100644 --- a/techlibs/coolrunner2/coolrunner2_fixup.cc +++ b/techlibs/coolrunner2/coolrunner2_fixup.cc @@ -23,6 +23,93 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cellname) +{ + RTLIL::Wire *outwire = nullptr; + + if (inwire == SigBit(true)) + { + // Constant 1 + outwire = module->addWire( + module->uniquify(stringf("$xc2fix$%s_BUF1_XOR_OUT", cellname))); + auto xor_cell = module->addCell( + module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)), + "\\MACROCELL_XOR"); + xor_cell->setParam("\\INVERT_OUT", true); + xor_cell->setPort("\\OUT", outwire); + } + else if (inwire == SigBit(false)) + { + // Constant 0 + outwire = module->addWire( + module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname))); + auto xor_cell = module->addCell( + module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)), + "\\MACROCELL_XOR"); + xor_cell->setParam("\\INVERT_OUT", false); + xor_cell->setPort("\\OUT", outwire); + } + else if (inwire == SigBit(RTLIL::State::Sx)) + { + // x; treat as 0 + log_warning("While buffering, changing x to 0 into cell %s\n", cellname); + outwire = module->addWire( + module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname))); + auto xor_cell = module->addCell( + module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)), + "\\MACROCELL_XOR"); + xor_cell->setParam("\\INVERT_OUT", false); + xor_cell->setPort("\\OUT", outwire); + } + else + { + auto inwire_name = inwire.wire->name.c_str(); + + outwire = module->addWire( + module->uniquify(stringf("$xc2fix$%s_BUF_XOR_OUT", inwire_name))); + + auto and_to_xor_wire = module->addWire( + module->uniquify(stringf("$xc2fix$%s_BUF_AND_OUT", inwire_name))); + + auto and_cell = module->addCell( + module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)), + "\\ANDTERM"); + and_cell->setParam("\\TRUE_INP", 1); + and_cell->setParam("\\COMP_INP", 0); + and_cell->setPort("\\OUT", and_to_xor_wire); + and_cell->setPort("\\IN", inwire); + and_cell->setPort("\\IN_B", SigSpec()); + + auto xor_cell = module->addCell( + module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)), + "\\MACROCELL_XOR"); + xor_cell->setParam("\\INVERT_OUT", false); + xor_cell->setPort("\\IN_PTC", and_to_xor_wire); + xor_cell->setPort("\\OUT", outwire); + } + + return outwire; +} + +RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire) +{ + auto inwire_name = inwire.wire->name.c_str(); + + auto outwire = module->addWire( + module->uniquify(stringf("$xc2fix$%s_BUF_AND_OUT", inwire_name))); + + auto and_cell = module->addCell( + module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)), + "\\ANDTERM"); + and_cell->setParam("\\TRUE_INP", 1); + and_cell->setParam("\\COMP_INP", 0); + and_cell->setPort("\\OUT", outwire); + and_cell->setPort("\\IN", inwire); + and_cell->setPort("\\IN_B", SigSpec()); + + return outwire; +} + struct Coolrunner2FixupPass : public Pass { Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { } void help() YS_OVERRIDE @@ -78,80 +165,352 @@ struct Coolrunner2FixupPass : public Pass { } } - // Start by buffering FF inputs. FF inputs can only come from either - // an IO pin or from an XOR. Otherwise AND/XOR cells need to be inserted. + // Find all the pterm outputs + pool sig_fed_by_pterm; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\ANDTERM") + { + auto output = sigmap(cell->getPort("\\OUT")[0]); + sig_fed_by_pterm.insert(output); + } + } + + // Find all the bufg outputs + pool sig_fed_by_bufg; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\BUFG") + { + auto output = sigmap(cell->getPort("\\O")[0]); + sig_fed_by_bufg.insert(output); + } + } + + // Find all the bufgsr outputs + pool sig_fed_by_bufgsr; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\BUFGSR") + { + auto output = sigmap(cell->getPort("\\O")[0]); + sig_fed_by_bufgsr.insert(output); + } + } + + // Find all the bufgts outputs + pool sig_fed_by_bufgts; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\BUFGTS") + { + auto output = sigmap(cell->getPort("\\O")[0]); + sig_fed_by_bufgts.insert(output); + } + } + + // This is used to fix the input -> FF -> output scenario + pool sig_fed_by_ibuf; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\IBUF") + { + auto output = sigmap(cell->getPort("\\O")[0]); + sig_fed_by_ibuf.insert(output); + } + } + + // Find all of the sinks for each output from an IBUF + dict> ibuf_fanouts; + for (auto cell : module->selected_cells()) + { + for (auto &conn : cell->connections()) + { + if (cell->input(conn.first)) + { + for (auto wire_in : sigmap(conn.second)) + { + if (sig_fed_by_ibuf[wire_in]) + { + auto existing_count = ibuf_fanouts[wire_in].first; + ibuf_fanouts[wire_in] = + std::pair(existing_count + 1, cell); + } + } + } + } + } + + dict ibuf_out_to_packed_reg_cell; + pool packed_reg_out; + for (auto x : ibuf_fanouts) + { + auto ibuf_out_wire = x.first; + auto fanout_count = x.second.first; + auto maybe_ff_cell = x.second.second; + + // The register can be packed with the IBUF only if it's + // actually a register and it's the only fanout. Otherwise, + // the pad-to-zia path has to be used up and the register + // can't be packed with the ibuf. + if (fanout_count == 1 && maybe_ff_cell->type.in( + "\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N", + "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) + { + SigBit input; + if (maybe_ff_cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) + input = sigmap(maybe_ff_cell->getPort("\\T")[0]); + else + input = sigmap(maybe_ff_cell->getPort("\\D")[0]); + SigBit output = sigmap(maybe_ff_cell->getPort("\\Q")[0]); + + if (input == ibuf_out_wire) + { + log("Found IBUF %s that can be packed with FF %s (type %s)\n", + ibuf_out_wire.wire->name.c_str(), + maybe_ff_cell->name.c_str(), + maybe_ff_cell->type.c_str()); + + ibuf_out_to_packed_reg_cell[ibuf_out_wire] = maybe_ff_cell; + packed_reg_out.insert(output); + } + } + } + for (auto cell : module->selected_cells()) { if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N", "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) { + // Buffering FF inputs. FF inputs can only come from either + // an IO pin or from an XOR. Otherwise AND/XOR cells need + // to be inserted. SigBit input; if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) input = sigmap(cell->getPort("\\T")[0]); else input = sigmap(cell->getPort("\\D")[0]); - if (!sig_fed_by_xor[input] && !sig_fed_by_io[input]) + // If the input wasn't an XOR nor an IO, then a buffer + // definitely needs to be added. + // Otherwise, if it is an IO, only leave unbuffered + // if we're being packed with the IO. + if ((!sig_fed_by_xor[input] && !sig_fed_by_io[input]) || + (sig_fed_by_io[input] && ibuf_out_to_packed_reg_cell[input] != cell)) { log("Buffering input to \"%s\"\n", cell->name.c_str()); - auto and_to_xor_wire = module->addWire(NEW_ID); - auto xor_to_ff_wire = module->addWire(NEW_ID); - - auto and_cell = module->addCell(NEW_ID, "\\ANDTERM"); - and_cell->setParam("\\TRUE_INP", 1); - and_cell->setParam("\\COMP_INP", 0); - and_cell->setPort("\\OUT", and_to_xor_wire); - and_cell->setPort("\\IN", input); - and_cell->setPort("\\IN_B", SigSpec()); - - auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", false); - xor_cell->setPort("\\IN_PTC", and_to_xor_wire); - xor_cell->setPort("\\OUT", xor_to_ff_wire); + auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str()); if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) cell->setPort("\\T", xor_to_ff_wire); else cell->setPort("\\D", xor_to_ff_wire); } + + // Buffering FF clocks. FF clocks can only come from either + // a pterm or a bufg. In some cases this will be handled + // in coolrunner2_sop (e.g. if clock is generated from + // AND-ing two signals) but not in all cases. + SigBit clock; + if (cell->type.in("\\LDCP", "\\LDCP_N")) + clock = sigmap(cell->getPort("\\G")[0]); + else + clock = sigmap(cell->getPort("\\C")[0]); + + if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock]) + { + log("Buffering clock to \"%s\"\n", cell->name.c_str()); + + auto pterm_to_ff_wire = makeptermbuffer(module, clock); + + if (cell->type.in("\\LDCP", "\\LDCP_N")) + cell->setPort("\\G", pterm_to_ff_wire); + else + cell->setPort("\\C", pterm_to_ff_wire); + } + + // Buffering FF set/reset. This can only come from either + // a pterm or a bufgsr. + SigBit set; + set = sigmap(cell->getPort("\\PRE")[0]); + if (set != SigBit(false)) + { + if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set]) + { + log("Buffering set to \"%s\"\n", cell->name.c_str()); + + auto pterm_to_ff_wire = makeptermbuffer(module, set); + + cell->setPort("\\PRE", pterm_to_ff_wire); + } + } + + SigBit reset; + reset = sigmap(cell->getPort("\\CLR")[0]); + if (reset != SigBit(false)) + { + if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset]) + { + log("Buffering reset to \"%s\"\n", cell->name.c_str()); + + auto pterm_to_ff_wire = makeptermbuffer(module, reset); + + cell->setPort("\\CLR", pterm_to_ff_wire); + } + } + + // Buffering FF clock enable + // FIXME: This doesn't fully fix PTC conflicts + // FIXME: Need to ensure constant enables are optimized out + if (cell->type.in("\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) + { + SigBit ce; + ce = sigmap(cell->getPort("\\CE")[0]); + if (!sig_fed_by_pterm[ce]) + { + log("Buffering clock enable to \"%s\"\n", cell->name.c_str()); + + auto pterm_to_ff_wire = makeptermbuffer(module, ce); + + cell->setPort("\\CE", pterm_to_ff_wire); + } + } } } - // Buffer IOBUFE inputs. This can only be fed from an XOR or FF. for (auto cell : module->selected_cells()) { if (cell->type == "\\IOBUFE") { + // Buffer IOBUFE inputs. This can only be fed from an XOR or FF. SigBit input = sigmap(cell->getPort("\\I")[0]); - // Special case: constant 0 and 1 are handled by xc2par - if (input == SigBit(true) || input == SigBit(false)) { - log("Not buffering constant IO to \"%s\"\n", cell->name.c_str()); - continue; - } - - if (!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) + if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) || + packed_reg_out[input]) { log("Buffering input to \"%s\"\n", cell->name.c_str()); - auto and_to_xor_wire = module->addWire(NEW_ID); - auto xor_to_io_wire = module->addWire(NEW_ID); - - auto and_cell = module->addCell(NEW_ID, "\\ANDTERM"); - and_cell->setParam("\\TRUE_INP", 1); - and_cell->setParam("\\COMP_INP", 0); - and_cell->setPort("\\OUT", and_to_xor_wire); - and_cell->setPort("\\IN", input); - and_cell->setPort("\\IN_B", SigSpec()); - - auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", false); - xor_cell->setPort("\\IN_PTC", and_to_xor_wire); - xor_cell->setPort("\\OUT", xor_to_io_wire); + auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str()); cell->setPort("\\I", xor_to_io_wire); } + + // Buffer IOBUFE enables. This can only be fed from a pterm + // or a bufgts. + if (cell->hasPort("\\E")) + { + SigBit oe; + oe = sigmap(cell->getPort("\\E")[0]); + if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe]) + { + log("Buffering output enable to \"%s\"\n", cell->name.c_str()); + + auto pterm_to_oe_wire = makeptermbuffer(module, oe); + + cell->setPort("\\E", pterm_to_oe_wire); + } + } + } + } + + // Now we have to fix up some cases where shared logic can + // cause XORs to have multiple fanouts to something other than + // pterms (which is not ok) + + // Find all the XOR outputs + dict xor_out_to_xor_cell; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\MACROCELL_XOR") + { + auto output = sigmap(cell->getPort("\\OUT")[0]); + xor_out_to_xor_cell[output] = cell; + } + } + + // Find all of the sinks for each output from an XOR + pool xor_fanout_once; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\ANDTERM") + continue; + + for (auto &conn : cell->connections()) + { + if (cell->input(conn.first)) + { + for (auto wire_in : sigmap(conn.second)) + { + auto xor_cell = xor_out_to_xor_cell[wire_in]; + if (xor_cell) + { + if (xor_fanout_once[wire_in]) + { + log("Additional fanout found for %s into %s (type %s), duplicating\n", + xor_cell->name.c_str(), + cell->name.c_str(), + cell->type.c_str()); + + auto new_xor_cell = module->addCell( + module->uniquify(xor_cell->name), xor_cell); + auto new_wire = module->addWire( + module->uniquify(wire_in.wire->name)); + new_xor_cell->setPort("\\OUT", new_wire); + cell->setPort(conn.first, new_wire); + } + xor_fanout_once.insert(wire_in); + } + } + } + } + } + + // Do the same fanout fixing for OR terms. By doing this + // after doing XORs, both pieces will be duplicated when necessary. + + // Find all the OR outputs + dict or_out_to_or_cell; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\ORTERM") + { + auto output = sigmap(cell->getPort("\\OUT")[0]); + or_out_to_or_cell[output] = cell; + } + } + + // Find all of the sinks for each output from an OR + pool or_fanout_once; + for (auto cell : module->selected_cells()) + { + for (auto &conn : cell->connections()) + { + if (cell->input(conn.first)) + { + for (auto wire_in : sigmap(conn.second)) + { + auto or_cell = or_out_to_or_cell[wire_in]; + if (or_cell) + { + if (or_fanout_once[wire_in]) + { + log("Additional fanout found for %s into %s (type %s), duplicating\n", + or_cell->name.c_str(), + cell->name.c_str(), + cell->type.c_str()); + + auto new_or_cell = module->addCell( + module->uniquify(or_cell->name), or_cell); + auto new_wire = module->addWire( + module->uniquify(wire_in.wire->name)); + new_or_cell->setPort("\\OUT", new_wire); + cell->setPort(conn.first, new_wire); + } + or_fanout_once.insert(wire_in); + } + } + } } } } diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc index 49ae8e21a..581477473 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cc +++ b/techlibs/coolrunner2/coolrunner2_sop.cc @@ -94,6 +94,8 @@ struct Coolrunner2SopPass : public Pass { auto sop_width = cell->getParam("\\WIDTH").as_int(); auto sop_table = cell->getParam("\\TABLE"); + auto sop_output_wire_name = sop_output.wire->name.c_str(); + // Check for a $_NOT_ at the output bool has_invert = false; if (not_cells.count(sop_output)) @@ -108,20 +110,15 @@ struct Coolrunner2SopPass : public Pass { } // Check for special P-term usage - bool is_special_pterm = false; - bool special_pterm_can_invert = false; - if (special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output)) - { - is_special_pterm = true; - if (!special_pterms_no_inv[sop_output].size()) - special_pterm_can_invert = true; - } + bool is_special_pterm = + special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output); // Construct AND cells pool intermed_wires; for (int i = 0; i < sop_depth; i++) { // Wire for the output - auto and_out = module->addWire(NEW_ID); + auto and_out = module->addWire( + module->uniquify(stringf("$xc2sop$%s_AND%d_OUT", sop_output_wire_name, i))); intermed_wires.insert(and_out); // Signals for the inputs @@ -140,7 +137,9 @@ struct Coolrunner2SopPass : public Pass { } // Construct the cell - auto and_cell = module->addCell(NEW_ID, "\\ANDTERM"); + auto and_cell = module->addCell( + module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)), + "\\ANDTERM"); and_cell->setParam("\\TRUE_INP", GetSize(and_in_true)); and_cell->setParam("\\COMP_INP", GetSize(and_in_comp)); and_cell->setPort("\\OUT", and_out); @@ -151,7 +150,9 @@ struct Coolrunner2SopPass : public Pass { if (sop_depth == 1) { // If there is only one term, don't construct an OR cell. Directly construct the XOR gate - auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR"); + auto xor_cell = module->addCell( + module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)), + "\\MACROCELL_XOR"); xor_cell->setParam("\\INVERT_OUT", has_invert); xor_cell->setPort("\\IN_PTC", *intermed_wires.begin()); xor_cell->setPort("\\OUT", sop_output); @@ -159,88 +160,61 @@ struct Coolrunner2SopPass : public Pass { // Special P-term handling if (is_special_pterm) { - if (!has_invert || special_pterm_can_invert) + // Can always connect the P-term directly if it's going + // into something invert-capable + for (auto x : special_pterms_inv[sop_output]) + { + std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin()); + + // If this signal is indeed inverted, flip the cell polarity + if (has_invert) + { + auto cell = std::get<0>(x); + if (cell->type == "\\FDCP") cell->type = "\\FDCP_N"; + else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP"; + else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N"; + else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP"; + else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N"; + else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE"; + else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N"; + else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP"; + else log_assert(!"Internal error! Bad cell type!"); + } + } + + // If it's going into something that's not invert-capable, + // connect it directly only if this signal isn't inverted + if (!has_invert) { - // Can connect the P-term directly to the special term sinks - for (auto x : special_pterms_inv[sop_output]) - std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin()); for (auto x : special_pterms_no_inv[sop_output]) std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin()); } - if (has_invert) - { - if (special_pterm_can_invert) - { - log_assert(special_pterms_no_inv[sop_output].size() == 0); - - for (auto x : special_pterms_inv[sop_output]) - { - auto cell = std::get<0>(x); - // Need to invert the polarity of the cell - if (cell->type == "\\FDCP") cell->type = "\\FDCP_N"; - else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP"; - else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N"; - else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP"; - else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N"; - else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE"; - else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N"; - else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP"; - else log_assert(!"Internal error! Bad cell type!"); - } - } - else - { - // Need to construct a feed-through term - auto feedthrough_out = module->addWire(NEW_ID); - auto feedthrough_cell = module->addCell(NEW_ID, "\\ANDTERM"); - feedthrough_cell->setParam("\\TRUE_INP", 1); - feedthrough_cell->setParam("\\COMP_INP", 0); - feedthrough_cell->setPort("\\OUT", feedthrough_out); - feedthrough_cell->setPort("\\IN", sop_output); - feedthrough_cell->setPort("\\IN_B", SigSpec()); - - for (auto x : special_pterms_inv[sop_output]) - std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out); - for (auto x : special_pterms_no_inv[sop_output]) - std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out); - } - } + // Otherwise, a feedthrough P-term has to be created. Leave that to happen + // in the coolrunner2_fixup pass. } } else { // Wire from OR to XOR - auto or_to_xor_wire = module->addWire(NEW_ID); + auto or_to_xor_wire = module->addWire( + module->uniquify(stringf("$xc2sop$%s_OR_OUT", sop_output_wire_name))); // Construct the OR cell - auto or_cell = module->addCell(NEW_ID, "\\ORTERM"); + auto or_cell = module->addCell( + module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)), + "\\ORTERM"); or_cell->setParam("\\WIDTH", sop_depth); or_cell->setPort("\\IN", intermed_wires); or_cell->setPort("\\OUT", or_to_xor_wire); // Construct the XOR cell - auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR"); + auto xor_cell = module->addCell( + module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)), + "\\MACROCELL_XOR"); xor_cell->setParam("\\INVERT_OUT", has_invert); xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire); xor_cell->setPort("\\OUT", sop_output); - - if (is_special_pterm) - { - // Need to construct a feed-through term - auto feedthrough_out = module->addWire(NEW_ID); - auto feedthrough_cell = module->addCell(NEW_ID, "\\ANDTERM"); - feedthrough_cell->setParam("\\TRUE_INP", 1); - feedthrough_cell->setParam("\\COMP_INP", 0); - feedthrough_cell->setPort("\\OUT", feedthrough_out); - feedthrough_cell->setPort("\\IN", sop_output); - feedthrough_cell->setPort("\\IN_B", SigSpec()); - - for (auto x : special_pterms_inv[sop_output]) - std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out); - for (auto x : special_pterms_no_inv[sop_output]) - std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out); - } } // Finally, remove the $sop cell diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index d940e5ac7..d5eeaf547 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -178,6 +178,7 @@ struct SynthCoolrunner2Pass : public ScriptPass run("dffinit -ff LDCP Q INIT"); run("dffinit -ff LDCP_N Q INIT"); run("coolrunner2_sop"); + run("clean"); run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO"); run("attrmvcp -attr src -attr LOC t:IOBUFE n:*"); run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*");