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Extend using A[1] to preserve don't care

This commit is contained in:
Eddie Hung 2019-07-09 12:35:41 -07:00
parent bee5d2b21a
commit b1a048a703
1 changed files with 9 additions and 1 deletions
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10
techlibs/xilinx/cells_map.v
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@ -203,7 +203,15 @@ module \$__XILINX_SHIFTX (A, B, Y);
MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y)); MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
end end
else if (A_WIDTH <= 4) begin else if (A_WIDTH <= 4) begin
wire [4-1:0] Ax = {{{4-A_WIDTH}{1'bx}}, A}; wire [4-1:0] Ax;
if (A_WIDTH == 4)
assign Ax = A;
else
// Rather than extend with 1'bx which gets flattened to 1'b0
// causing the "don't care" status to get lost, extend with
// the same driver of F7B.I0 so that we can optimise F7B away
// later
assign Ax = {A[1], A};
\$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y)); \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
end end
else if (A_WIDTH <= 8) begin else if (A_WIDTH <= 8) begin