mirror of https://github.com/YosysHQ/yosys.git
cellmatch: Rename the special design to `$cellmatch`
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@ -136,7 +136,7 @@ struct CellmatchPass : Pass {
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log("selected modules and a module from the secondary design <design>. For every such\n");
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log("correspondence found, a techmap rule is generated for mapping instances of the\n");
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log("former to instances of the latter. This techmap rule is saved in yet another\n");
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log("design called '$cellmatch_map', which is created if non-existent.\n");
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log("design called '$cellmatch', which is created if non-existent.\n");
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log("\n");
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log("This pass restricts itself to combinational modules. Modules are functionally\n");
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log("equivalent as long as their truth tables are identical upto a permutation of\n");
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@ -192,7 +192,7 @@ struct CellmatchPass : Pass {
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targets[p_classes].push_back(Target{m, luts});
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}
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auto r = saved_designs.emplace("$cellmatch_map", nullptr);
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auto r = saved_designs.emplace("$cellmatch", nullptr);
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if (r.second)
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r.first->second = new Design;
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Design *map_design = r.first->second;
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@ -61,7 +61,7 @@ prep
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cellmatch -lib gatelib FA A:gate
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design -save gold
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techmap -map %$cellmatch_map
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techmap -map %$cellmatch
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design -save gate
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select -assert-none ripple_carry/t:FA
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