mirror of https://github.com/YosysHQ/yosys.git
Make small build links, and support verific small build
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parent
b74d33d1b8
commit
b11449badb
11
Makefile
11
Makefile
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@ -679,12 +679,8 @@ OBJS += libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o
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OBJS += libs/sha1/sha1.o
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OBJS += libs/sha1/sha1.o
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ifneq ($(SMALL),1)
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OBJS += libs/json11/json11.o
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OBJS += libs/json11/json11.o
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OBJS += libs/subcircuit/subcircuit.o
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OBJS += libs/ezsat/ezsat.o
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OBJS += libs/ezsat/ezsat.o
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OBJS += libs/ezsat/ezminisat.o
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OBJS += libs/ezsat/ezminisat.o
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@ -699,6 +695,10 @@ OBJS += libs/fst/fastlz.o
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OBJS += libs/fst/lz4.o
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OBJS += libs/fst/lz4.o
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endif
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endif
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ifneq ($(SMALL),1)
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OBJS += libs/subcircuit/subcircuit.o
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include $(YOSYS_SRC)/frontends/*/Makefile.inc
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include $(YOSYS_SRC)/frontends/*/Makefile.inc
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include $(YOSYS_SRC)/passes/*/Makefile.inc
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include $(YOSYS_SRC)/passes/*/Makefile.inc
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include $(YOSYS_SRC)/backends/*/Makefile.inc
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include $(YOSYS_SRC)/backends/*/Makefile.inc
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@ -707,6 +707,9 @@ include $(YOSYS_SRC)/techlibs/*/Makefile.inc
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else
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else
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include $(YOSYS_SRC)/frontends/verilog/Makefile.inc
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include $(YOSYS_SRC)/frontends/verilog/Makefile.inc
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ifeq ($(ENABLE_VERIFIC),1)
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include $(YOSYS_SRC)/frontends/verific/Makefile.inc
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endif
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include $(YOSYS_SRC)/frontends/rtlil/Makefile.inc
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include $(YOSYS_SRC)/frontends/rtlil/Makefile.inc
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include $(YOSYS_SRC)/frontends/ast/Makefile.inc
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include $(YOSYS_SRC)/frontends/ast/Makefile.inc
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include $(YOSYS_SRC)/frontends/blif/Makefile.inc
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include $(YOSYS_SRC)/frontends/blif/Makefile.inc
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