From b0c4add642f23f899f5aac69c5970d9e34e1a921 Mon Sep 17 00:00:00 2001 From: Lofty Date: Fri, 1 Mar 2024 13:41:25 +0100 Subject: [PATCH] Added lutram --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/cells_bb.v | 50 ++++++++++++------------ techlibs/nanoxplore/cells_map.v | 12 ++++++ techlibs/nanoxplore/cells_sim.v | 51 +++++++++++++++++++++++++ techlibs/nanoxplore/drams.txt | 27 +++++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 41 ++++++++++++++++++-- tests/arch/nanoxplore/lutram.ys | 8 ++++ 7 files changed, 161 insertions(+), 29 deletions(-) create mode 100644 techlibs/nanoxplore/drams.txt create mode 100644 tests/arch/nanoxplore/lutram.ys diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 0f7bcdbed..d7331f5de 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -6,3 +6,4 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt)) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 7ebad4ae8..6aa981529 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -32930,31 +32930,31 @@ module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA); parameter wck_edge = 1'b0; endmodule -(* blackbox *) -module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA); - input [35:0] I; - output [35:0] O; - input [4:0] RA; - input [4:0] WA; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); - input [17:0] I; - output [17:0] O; - input [5:0] RA; - input [5:0] WA; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter wck_edge = 1'b0; -endmodule +//(* blackbox *) +//module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA); +// input [35:0] I; +// output [35:0] O; +// input [4:0] RA; +// input [4:0] WA; +// input WCK; +// input WE; +// input WEA; +// parameter mem_ctxt = ""; +// parameter wck_edge = 1'b0; +//endmodule +// +//(* blackbox *) +//module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); +// input [17:0] I; +// output [17:0] O; +// input [5:0] RA; +// input [5:0] WA; +// input WCK; +// input WE; +// input WEA; +// parameter mem_ctxt = ""; +// parameter wck_edge = 1'b0; +//endmodule (* blackbox *) module SMACC24x18_1DSP(clk, rst, A, B, Z); diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index efa2a2af5..9728922f3 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -66,3 +66,15 @@ endmodule module \$_SDFF_NP1_ (input D, C, R, output Q); NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule + +module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); +endmodule + +module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); +endmodule diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 1f04b216e..2a4b5b00f 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -9,6 +9,7 @@ assign O = I1 ? s3[1] : s3[0]; endmodule +(* abc9_box, lib_whitebox *) module NX_DFF(input I, CK, L, R, output reg O); parameter dff_ctxt = 1'bx; @@ -34,8 +35,58 @@ always @(posedge clock, posedge async_reset) endmodule +(* abc9_box, lib_whitebox *) module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO); parameter add_carry = 0; assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI; + +endmodule + +(* abc9_box, lib_whitebox *) +module NX_XRFB_64x18(input WCK, input [17:0] I, input [5:0] RA, WA, input WE, WEA, output [17:0] O); + +parameter wck_edge = 1'b0; +parameter mem_ctxt = 1152'b0; + +reg [17:0] mem [63:0]; + +integer i; +initial begin + for (i = 0; i < 64; i = i + 1) + mem[i] = mem_ctxt[18*i +: 18]; +end + +wire clock = WCK ^ wck_edge; + +always @(posedge clock) + if (WE && WEA) + mem[WA] <= I; + +assign O = mem[RA]; + +endmodule + +(* abc9_box, lib_whitebox *) +module NX_XRFB_32x36(input WCK, input [35:0] I, input [4:0] RA, WA, input WE, WEA, output [35:0] O); + +parameter wck_edge = 1'b0; +parameter mem_ctxt = 1152'b0; + +reg [35:0] mem [31:0]; + +integer i; +initial begin + for (i = 0; i < 32; i = i + 1) + mem[i] = mem_ctxt[36*i +: 36]; +end + +wire clock = WCK ^ wck_edge; + +always @(posedge clock) + if (WE && WEA) + mem[WA] <= I; + +assign O = mem[RA]; + endmodule diff --git a/techlibs/nanoxplore/drams.txt b/techlibs/nanoxplore/drams.txt new file mode 100644 index 000000000..370b62b16 --- /dev/null +++ b/techlibs/nanoxplore/drams.txt @@ -0,0 +1,27 @@ +ram distributed $__NX_XRFB_64x18_ { + abits 6; + width 18; + cost 10; + init no_undef; + prune_rom; + + port sw "W" { + clock anyedge; + } + port ar "R" { + } +} + +ram distributed $__NX_XRFB_32x36_ { + abits 5; + width 36; + cost 10; + init no_undef; + prune_rom; + + port sw "W" { + clock anyedge; + } + port ar "R" { + } +} \ No newline at end of file diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index b37bed164..97c4a21a4 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -73,6 +73,18 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nocy\n"); log(" do not map adders to CY cells\n"); log("\n"); + log(" -nolutram\n"); + log(" do not use LUT RAM cells in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use block RAM cells in output netlist\n"); + log("\n"); + log(" -nodsp\n"); + log(" do not map multipliers to NX_DSP cells\n"); + log("\n"); + log(" -noiopad\n"); + log(" do not instantiate IO buffers\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -80,7 +92,7 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy; + bool flatten, abc9, nocy, nolutram, nobram, nodsp, noiopad; void clear_flags() override { @@ -90,6 +102,10 @@ struct SynthNanoXplorePass : public ScriptPass flatten = true; abc9 = false; nocy = false; + nolutram = false; + nobram = false; + nodsp = false; + noiopad = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -136,12 +152,28 @@ struct SynthNanoXplorePass : public ScriptPass nocy = true; continue; } + if (args[argidx] == "-nolutram") { + nolutram = true; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } + if (args[argidx] == "-noiopad") { + noiopad = true; + continue; + } break; } extra_args(args, argidx, design); if (family.empty()) { - log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); + //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); family = "ultra"; } @@ -190,8 +222,9 @@ struct SynthNanoXplorePass : public ScriptPass run("opt_clean"); } - if (check_label("map_ram")) - { + if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { + run("memory_libmap -lib +/nanoxplore/drams.txt"); + run("techmap -map +/nanoxplore/cells_map.v t:$__NX_XRFB_32x36_ t:$__NX_XRFB_64x18_"); } if (check_label("map_ffram")) diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys new file mode 100644 index 000000000..97035b64c --- /dev/null +++ b/tests/arch/nanoxplore/lutram.ys @@ -0,0 +1,8 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +synth_nanoxplore -noiopad +cd lutram_1w1r +select -assert-count 1 t:NX_XRFB_64x18 +select -assert-count 8 t:NX_DFF +select -assert-none t:NX_XRFB_64x18 t:NX_DFF %% t:* %D +