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Merge pull request #1429 from YosysHQ/clifford/checkmapped 

Add "check -mapped"
This commit is contained in:
Clifford Wolf 2019-10-03 11:50:53 +02:00 committed by GitHub
parent e0a6742935 3e27b2846b
commit afdc990595
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 56 additions and 27 deletions
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1
CHANGELOG
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@ -50,6 +50,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
- "synth_ice40 -dsp" to infer DSP blocks - "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx - Added latch support to synth_xilinx
- Added "check -mapped"
Yosys 0.8 .. Yosys 0.9 Yosys 0.8 .. Yosys 0.9
---------------------- ----------------------

82
passes/cmds/check.cc
View File

@ -41,14 +41,24 @@ struct CheckPass : public Pass {
log("\n"); log("\n");
log(" - used wires that do not have a driver\n"); log(" - used wires that do not have a driver\n");
log("\n"); log("\n");
log("When called with -noinit then this command also checks for wires which have\n"); log("Options:\n");
log("the 'init' attribute set.\n");
log("\n"); log("\n");
log("When called with -initdrv then this command also checks for wires which have\n"); log(" -noinit\n");
log("the 'init' attribute set and aren't driven by a FF cell type.\n"); log(" Also check for wires which have the 'init' attribute set.\n");
log("\n"); log("\n");
log("When called with -assert then the command will produce an error if any\n"); log(" -initdrv\n");
log("problems are found in the current design.\n"); log(" Also check for wires that have the 'init' attribute set and are not\n");
log(" driven by an FF cell type.\n");
log("\n");
log(" -mapped\n");
log(" Also check for internal cells that have not been mapped to cells of the\n");
log(" target architecture.\n");
log("\n");
log(" -allow-tbuf\n");
log(" Modify the -mapped behavior to still allow $_TBUF_ cells.\n");
log("\n");
log(" -assert\n");
log(" Produce a runtime error if any problems are found in the current design.\n");
log("\n"); log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -56,6 +66,8 @@ struct CheckPass : public Pass {
int counter = 0; int counter = 0;
bool noinit = false; bool noinit = false;
bool initdrv = false; bool initdrv = false;
bool mapped = false;
bool allow_tbuf = false;
bool assert_mode = false; bool assert_mode = false;
size_t argidx; size_t argidx;
@ -68,6 +80,14 @@ struct CheckPass : public Pass {
initdrv = true; initdrv = true;
continue; continue;
} }
if (args[argidx] == "-mapped") {
mapped = true;
continue;
}
if (args[argidx] == "-allow-tbuf") {
allow_tbuf = true;
continue;
}
if (args[argidx] == "-assert") { if (args[argidx] == "-assert") {
assert_mode = true; assert_mode = true;
continue; continue;
@ -135,29 +155,37 @@ struct CheckPass : public Pass {
TopoSort<string> topo; TopoSort<string> topo;
for (auto cell : module->cells()) for (auto cell : module->cells())
for (auto &conn : cell->connections()) { {
SigSpec sig = sigmap(conn.second); if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
bool logic_cell = yosys_celltypes.cell_evaluable(cell->type); if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
if (cell->input(conn.first)) log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type));
for (auto bit : sig) counter++;
if (bit.wire) { cell_allowed:;
}
for (auto &conn : cell->connections()) {
SigSpec sig = sigmap(conn.second);
bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
if (cell->input(conn.first))
for (auto bit : sig)
if (bit.wire) {
if (logic_cell)
topo.edge(stringf("wire %s", log_signal(bit)),
stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
used_wires.insert(bit);
}
if (cell->output(conn.first))
for (int i = 0; i < GetSize(sig); i++) {
if (logic_cell) if (logic_cell)
topo.edge(stringf("wire %s", log_signal(bit)), topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
stringf("cell %s (%s)", log_id(cell), log_id(cell->type))); stringf("wire %s", log_signal(sig[i])));
used_wires.insert(bit); if (sig[i].wire)
wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
log_id(conn.first), i, log_id(cell), log_id(cell->type)));
} }
if (cell->output(conn.first)) if (!cell->input(conn.first) && cell->output(conn.first))
for (int i = 0; i < GetSize(sig); i++) { for (auto bit : sig)
if (logic_cell) if (bit.wire) wire_drivers_count[bit]++;
topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)), }
stringf("wire %s", log_signal(sig[i])));
if (sig[i].wire)
wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
log_id(conn.first), i, log_id(cell), log_id(cell->type)));
}
if (!cell->input(conn.first) && cell->output(conn.first))
for (auto bit : sig)
if (bit.wire) wire_drivers_count[bit]++;
} }
pool<SigBit> init_bits; pool<SigBit> init_bits;