mirror of https://github.com/YosysHQ/yosys.git
Fix tabulation
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@ -366,10 +366,6 @@ struct AigerFrontend : public Frontend {
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log("\n");
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log(" -module_name <module_name>\n");
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log(" Name of module to be created (default: <filename>)"
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log("\n");
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log(" -clk_name <wire_name>\n");
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log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
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log(" this name (default: clk)\n");
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#ifdef _WIN32
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"top" // FIXME
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#else
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@ -377,6 +373,10 @@ struct AigerFrontend : public Frontend {
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#endif
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")\n");
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log("\n");
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log(" -clk_name <wire_name>\n");
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log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
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log(" this name (default: clk)\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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