Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings

ice40: reduce ABC9 internal fanout warnings with a param for CI->I3

passes/pmgen/ice40_wrapcarry.cc

@@ -42,11 +42,19 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
 
 	cell->setPort("\\A", st.carry->getPort("\\I0"));
 	cell->setPort("\\B", st.carry->getPort("\\I1"));
-	cell->setPort("\\CI", st.carry->getPort("\\CI"));
+	auto CI = st.carry->getPort("\\CI");
+	cell->setPort("\\CI", CI);
 	cell->setPort("\\CO", st.carry->getPort("\\CO"));
 
 	cell->setPort("\\I0", st.lut->getPort("\\I0"));
-	cell->setPort("\\I3", st.lut->getPort("\\I3"));
+	auto I3 = st.lut->getPort("\\I3");
+	if (pm.sigmap(CI) == pm.sigmap(I3)) {
+		cell->setParam("\\I3_IS_CI", State::S1);
+		I3 = State::Sx;
+	}
+	else
+		cell->setParam("\\I3_IS_CI", State::S0);
+	cell->setPort("\\I3", I3);
 	cell->setPort("\\O", st.lut->getPort("\\O"));
 	cell->setParam("\\LUT", st.lut->getParam("\\LUT_INIT"));
 
@@ -118,7 +126,8 @@ struct Ice40WrapCarryPass : public Pass {
 					auto lut = module->addCell(lut_name, ID($lut));
 					lut->setParam(ID(WIDTH), 4);
 					lut->setParam(ID(LUT), cell->getParam(ID(LUT)));
-					lut->setPort(ID(A), {cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), cell->getPort(ID(I3)) });
+					auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
+					lut->setPort(ID(A), {cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), I3 });
 					lut->setPort(ID(Y), cell->getPort(ID(O)));
 
 					Const src;

techlibs/ice40/abc9_model.v

@@ -9,6 +9,8 @@ module \$__ICE40_CARRY_WRAPPER (
 	input I0, I3
 );
 	parameter LUT = 0;
+	parameter I3_IS_CI = 0;
+	wire I3_OR_CI = I3_IS_CI ? CI : I3;
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
@@ -21,7 +23,7 @@ module \$__ICE40_CARRY_WRAPPER (
 		.I0(I0),
 		.I1(A),
 		.I2(B),
-		.I3(I3),
+		.I3(I3_OR_CI),
 		.O(O)
 	);
 endmodule

techlibs/ice40/abc9_u.box

@@ -6,13 +6,12 @@
 
 # Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
 #                                 SB_LUT4+SB_CARRY)
-# Outputs: O, CO
 #   (Exception: carry chain input/output must be the
 #        last input and output and the entire bus has been
 #        moved there overriding the otherwise
 #        alphabetical ordering)
 # name                 ID  w/b ins outs
 $__ICE40_CARRY_WRAPPER 1   1   5   2
-#A  B   I0  I3  CI
+#A   B    I0   I3  CI
 1231 1205 1285 874 874 # O
 675  609  -    -   278 # CO

techlibs/ice40/arith_map.v

@@ -49,13 +49,14 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			//    A[1]: 1100 1100 1100 1100
 			//    A[2]: 1111 0000 1111 0000
 			//    A[3]: 1111 1111 0000 0000
-			.LUT(16'b 0110_1001_1001_0110)
+			.LUT(16'b 0110_1001_1001_0110),
+			.I3_IS_CI(1'b1)
 		) carry (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
 			.I0(1'b0),
-			.I3(C[i]),
+			.I3(1'bx),
 			.CO(CO[i]),
 			.O(Y[i])
 		);

techlibs/ice40/ice40_opt.cc

@@ -139,7 +139,8 @@ static void run_ice40_opts(Module *module)
 				log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
-				cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
+				auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
+				cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 });
 				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
@@ -148,6 +149,7 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
 				cell->setParam("\\WIDTH", 4);
+				cell->unsetParam("\\I3_IS_CI");
 			}
 			continue;
 		}

tests/arch/ice40/ice40_opt.ys

@@ -1,23 +1,3 @@
-read_verilog -icells -formal <<EOT
-module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
-  parameter LUT = 0;
-  SB_CARRY carry (
-    .I0(A),
-    .I1(B),
-    .CI(CI),
-    .CO(CO)
-  );
-  \$lut #(
-    .WIDTH(4),
-    .LUT(LUT)
-  ) lut (
-    .A({I0,A,B,I3}),
-    .Y(O)
-  );
-endmodule
-EOT
-design -stash unmap
-
 read_verilog -icells -formal <<EOT
 module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
@@ -26,13 +6,14 @@ module top(input CI, I0, output [1:0] CO, output O);
 		//    A[1]: 1100 1100 1100 1100
 		//    A[2]: 1111 0000 1111 0000
 		//    A[3]: 1111 1111 0000 0000
-		.LUT(~16'b 0110_1001_1001_0110)
+		.LUT(~16'b 0110_1001_1001_0110),
+		.I3_IS_CI(1'b1)
 	) u0 (
 		.A(A),
 		.B(B),
 		.CI(CI),
 		.I0(I0),
-		.I3(CI),
+		.I3(1'bx),
 		.CO(CO[0]),
 		.O(O)
 	);
@@ -40,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
 endmodule
 EOT
 
-equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
+equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
 select -assert-count 1 t:*
 select -assert-count 1 t:$lut