mirror of https://github.com/YosysHQ/yosys.git
Merge 8e508f2a2a
into 1717a0b9c0
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commit
af64198c2e
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@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
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{
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for (auto *cell : module->selected_cells()) {
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for (auto ¶meter : cell->parameters) {
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for (auto bit : parameter.second) {
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for (auto &bit : parameter.second.bits()) {
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if (bit > RTLIL::State::S1)
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bit = worker.next_bit();
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}
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@ -0,0 +1,10 @@
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module foo #(parameter [1:0] a) (output [1:0] o);
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assign o = a;
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endmodule
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module top(output [1:0] o);
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foo #(2'b0x) foo(o);
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always_comb begin
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assert(o == 2'b00);
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end
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endmodule
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@ -0,0 +1,8 @@
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read_verilog -sv setundef.sv
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setundef -zero -params
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hierarchy -top top
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flatten
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proc
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async2sync
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write_json
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sat -seq 5 -prove-asserts
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