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Kamil Rakoczy 2024-11-28 00:10:04 +01:00 committed by GitHub
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3 changed files with 19 additions and 1 deletions

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@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
{
for (auto *cell : module->selected_cells()) {
for (auto &parameter : cell->parameters) {
for (auto bit : parameter.second) {
for (auto &bit : parameter.second.bits()) {
if (bit > RTLIL::State::S1)
bit = worker.next_bit();
}

10
tests/various/setundef.sv Normal file
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@ -0,0 +1,10 @@
module foo #(parameter [1:0] a) (output [1:0] o);
assign o = a;
endmodule
module top(output [1:0] o);
foo #(2'b0x) foo(o);
always_comb begin
assert(o == 2'b00);
end
endmodule

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@ -0,0 +1,8 @@
read_verilog -sv setundef.sv
setundef -zero -params
hierarchy -top top
flatten
proc
async2sync
write_json
sat -seq 5 -prove-asserts