riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

opt_expr: fix missing brace

This commit is contained in:
Eddie Hung 2020-03-20 09:17:53 -07:00
parent 81ca776ea4
commit af16ca9dd4
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/opt/opt_expr.cc
View File

@ -502,7 +502,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
SigBit sig_b = assign_map(cell->getPort(ID::B)); SigBit sig_b = assign_map(cell->getPort(ID::B));
if (!sig_a.wire) if (!sig_a.wire)
std::swap(sig_a, sig_b); std::swap(sig_a, sig_b);
if (sig_b == State::S0 || sig_b == State::S1) if (sig_b == State::S0 || sig_b == State::S1) {
if (cell->type.in(ID($xor), ID($_XOR_))) { if (cell->type.in(ID($xor), ID($_XOR_))) {
cover("opt.opt_expr.xor_buffer"); cover("opt.opt_expr.xor_buffer");
replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a); replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
@ -510,9 +510,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
if (cell->type.in(ID($xnor), ID($_XNOR_))) { if (cell->type.in(ID($xnor), ID($_XNOR_))) {
cover("opt.opt_expr.xnor_buffer"); cover("opt.opt_expr.xnor_buffer");
replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a)); replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
goto next_cell; goto next_cell;
} }
log_abort();
}
} }
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) && if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) &&