mirror of https://github.com/YosysHQ/yosys.git
alumacc: undo accidental commit
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da134701cd
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af0e7637a2
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@ -397,21 +397,18 @@ struct AlumaccWorker
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{
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log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type));
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bool cmp_less = false; //cell->type.in(ID($lt), ID($le));
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bool cmp_equal = false; //cell->type.in(ID($le), ID($ge));
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bool cmp_less = cell->type.in(ID($lt), ID($le));
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bool cmp_equal = cell->type.in(ID($le), ID($ge));
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bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
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RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
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RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
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RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
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if (cell->type.in(ID($lt), ID($ge)))
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if (B < A && GetSize(B)) {
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cmp_less = !cmp_less;
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std::swap(A, B);
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//if (B < A && GetSize(B)) {
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// cmp_less = !cmp_less;
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// std::swap(A, B);
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//}
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}
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alunode_t *n = nullptr;
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@ -435,12 +432,6 @@ struct AlumaccWorker
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log(" merged with %s.\n", log_id(n->cells.front()));
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}
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if (cell->type.in(ID($le), ID($ge))) {
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SigSpec YY = module->addWire(NEW_ID, GetSize(Y));
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module->addNot(NEW_ID, YY, Y);
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Y = YY;
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}
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n->cells.push_back(cell);
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n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, Y));
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}
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