riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

alumacc: undo accidental commit

This commit is contained in:
Eddie Hung 2020-01-22 20:54:03 -08:00
parent da134701cd
commit af0e7637a2
1 changed files with 5 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
passes/techmap/alumacc.cc
View File

@ -397,21 +397,18 @@ struct AlumaccWorker
{ {
log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type)); log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type));
bool cmp_less = false; //cell->type.in(ID($lt), ID($le)); bool cmp_less = cell->type.in(ID($lt), ID($le));
bool cmp_equal = false; //cell->type.in(ID($le), ID($ge)); bool cmp_equal = cell->type.in(ID($le), ID($ge));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(ID::A)); RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B)); RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y)); RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
if (cell->type.in(ID($lt), ID($ge))) if (B < A && GetSize(B)) {
cmp_less = !cmp_less;
std::swap(A, B); std::swap(A, B);
}
//if (B < A && GetSize(B)) {
// cmp_less = !cmp_less;
// std::swap(A, B);
//}
alunode_t *n = nullptr; alunode_t *n = nullptr;
@ -435,12 +432,6 @@ struct AlumaccWorker
log(" merged with %s.\n", log_id(n->cells.front())); log(" merged with %s.\n", log_id(n->cells.front()));
} }
if (cell->type.in(ID($le), ID($ge))) {
SigSpec YY = module->addWire(NEW_ID, GetSize(Y));
module->addNot(NEW_ID, YY, Y);
Y = YY;
}
n->cells.push_back(cell); n->cells.push_back(cell);
n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, Y)); n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, Y));
} }