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Ooops AREG and BREG to default to -1

This commit is contained in:
Eddie Hung 2019-09-27 11:57:53 -07:00
parent 26657037b8
commit aebbfffd71
1 changed files with 2 additions and 2 deletions
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4
passes/pmgen/xilinx_dsp_cascade.pmg
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@ -146,7 +146,7 @@ code next
endcode endcode
code argQ clock AREG code argQ clock AREG
AREG = 0; AREG = -1;
if (next) { if (next) {
Cell *prev = std::get<0>(chain.back()); Cell *prev = std::get<0>(chain.back());
if (param(prev, \AREG, 2).as_int() > 0 && if (param(prev, \AREG, 2).as_int() > 0 &&
@ -175,7 +175,7 @@ reject_AREG: ;
endcode endcode
code argQ clock BREG code argQ clock BREG
BREG = 0; BREG = -1;
if (next) { if (next) {
Cell *prev = std::get<0>(chain.back()); Cell *prev = std::get<0>(chain.back());
if (param(prev, \BREG, 2).as_int() > 0 && if (param(prev, \BREG, 2).as_int() > 0 &&