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Fixed bit-extending in $mux argument (use $bu0 instead of $pos)

This commit is contained in:
Clifford Wolf 2014-02-26 21:32:19 +01:00
parent aaaa604853
commit ae5032af84
1 changed files with 5 additions and 5 deletions
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10
frontends/ast/genrtlil.cc
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@ -83,7 +83,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
} }
// helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval) // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed) static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed, std::string celltype)
{ {
if (width <= sig.width) { if (width <= sig.width) {
sig.extend(width, is_signed); sig.extend(width, is_signed);
@ -96,7 +96,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
RTLIL::Cell *cell = new RTLIL::Cell; RTLIL::Cell *cell = new RTLIL::Cell;
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
cell->name = sstr.str(); cell->name = sstr.str();
cell->type = "$pos"; cell->type = celltype;
current_module->cells[cell->name] = cell; current_module->cells[cell->name] = cell;
RTLIL::Wire *wire = new RTLIL::Wire; RTLIL::Wire *wire = new RTLIL::Wire;
@ -1041,7 +1041,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = arg.width; int width = arg.width;
if (width_hint > 0) { if (width_hint > 0) {
width = width_hint; width = width_hint;
widthExtend(this, arg, width, is_signed); widthExtend(this, arg, width, is_signed, "$pos");
} }
return uniop2rtlil(this, type_name, width, arg); return uniop2rtlil(this, type_name, width, arg);
} }
@ -1196,8 +1196,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = std::max(val1.width, val2.width); int width = std::max(val1.width, val2.width);
is_signed = children[1]->is_signed && children[2]->is_signed; is_signed = children[1]->is_signed && children[2]->is_signed;
widthExtend(this, val1, width, is_signed); widthExtend(this, val1, width, is_signed, "$bu0");
widthExtend(this, val2, width, is_signed); widthExtend(this, val2, width, is_signed, "$bu0");
RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2); RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);