mirror of https://github.com/YosysHQ/yosys.git
abc9 to output some more info
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@ -343,7 +343,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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else
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else
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abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
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abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
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abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str());
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abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
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if (!script_file.empty()) {
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if (!script_file.empty()) {
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if (script_file[0] == '+') {
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if (script_file[0] == '+') {
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@ -388,6 +388,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
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abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
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abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
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abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
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abc_script += "; &ps -l -s";
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abc_script = add_echos_to_abc_cmd(abc_script);
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abc_script = add_echos_to_abc_cmd(abc_script);
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for (size_t i = 0; i+1 < abc_script.size(); i++)
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for (size_t i = 0; i+1 < abc_script.size(); i++)
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