mirror of https://github.com/YosysHQ/yosys.git
Fixed $memwr/$memrd order in memory_dff
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@ -169,12 +169,14 @@ static void handle_module(RTLIL::Module *module, bool flag_wr_only)
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if (cell->type == "$dff")
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dff_cells.push_back(cell);
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for (auto cell : module->selected_cells()) {
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for (auto cell : module->selected_cells())
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if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
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handle_wr_cell(module, dff_cells, cell);
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if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
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if (!flag_wr_only)
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for (auto cell : module->selected_cells())
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if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
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handle_rd_cell(module, dff_cells, cell);
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}
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}
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struct MemoryDffPass : public Pass {
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