riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

generate only simple assignments in verilog backend

This commit is contained in:
Miodrag Milanovic 2020-11-25 17:43:28 +01:00
parent cf67e6a397
commit addc493e8d
1 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
backends/verilog/verilog_backend.cc
View File

@ -1546,11 +1546,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{ {
f << stringf("%s" "assign ", indent.c_str()); int offset = 0;
dump_sigspec(f, left); for (auto &chunk : left.chunks()) {
f << stringf(" = "); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, right); dump_sigspec(f, chunk);
f << stringf(";\n"); f << stringf(" = ");
dump_sigspec(f, right.extract(offset, GetSize(chunk)));
f << stringf(";\n");
offset += GetSize(chunk);
}
} }
void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw); void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw);