mirror of https://github.com/YosysHQ/yosys.git
Add pmgen slices and choices
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
fe1b2337fd
commit
adb81ba386
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@ -27,6 +27,7 @@ Yosys 0.9 .. Yosys 0.9-dev
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- Added "opt_share" pass, run as part of "opt -full"
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- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
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- Removed "ice40_unlut"
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- Improvements in pmgen: slices, choices, define, generate
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Yosys 0.8 .. Yosys 0.8-dev
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--------------------------
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@ -178,6 +178,45 @@ evaluates to `false`.
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The `semioptional` statement marks matches that must match if at least one
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matching cell exists, but if no matching cell exists it is set to `nullptr`.
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Slices and choices
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------------------
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Cell matches can contain "slices" and "choices". Slices can be used to
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create matches for different sections of a cell. For example:
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state <int> pmux_slice
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match pmux
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select pmux->type == $pmux
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slice idx GetSize(port(pmux, \S))
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index <SigBit> port(pmux, \S)[idx] === port(eq, \Y)
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set pmux_slice idx
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endmatch
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The first argument to `slice` is the local variable name used to identify the
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slice. The second argument is the number of slices that should be created for
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this cell. The `set` statement can be used to copy that index indo a state
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variable so that later matches and/or code blocks can refer to it.
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A similar mechanism is "choices", where a list of options is given as
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second argument, and the matcher will iterate over those options:
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state <SigSpec> foo bar
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state <IdString> eq_ab eq_ba
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match eq
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select eq->type == $eq
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choice <IdString> AB {\A, \B}
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(eq, AB) === foo
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index <SigSpec> port(eq, BA) === bar
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set eq_ab AB
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set eq_ba BA
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generate
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Notice how `define` can be used to define additional local variables similar
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to the loop variables defined by `slice` and `choice`.
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Additional code
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---------------
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@ -326,7 +365,7 @@ test-case generation. For example:
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match mul
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...
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generate 10
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generate 10 0
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SigSpec Y = port(ff, \D);
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SigSpec A = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
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SigSpec B = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
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@ -335,8 +374,11 @@ test-case generation. For example:
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The expression `rng(n)` returns a non-negative integer less than `n`.
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The argument to `generate` is the chance of this generate block being executed
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when the match block did not match anything, in percent.
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The first argument to `generate` is the chance of this generate block being
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executed when the match block did not match anything, in percent.
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The second argument to `generate` is the chance of this generate block being
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executed when the match block did match something, in percent.
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The special statement `finish` can be used within generate blocks to terminate
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the current pattern matcher run.
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@ -207,9 +207,10 @@ def process_pmgfile(f, filename):
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state_types[current_pattern][line[1]] = "Cell*";
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block["if"] = list()
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block["select"] = list()
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block["setup"] = list()
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block["index"] = list()
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block["filter"] = list()
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block["sets"] = list()
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block["optional"] = False
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block["semioptional"] = False
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@ -228,7 +229,22 @@ def process_pmgfile(f, filename):
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if a[0] == "select":
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b = l.lstrip()[6:]
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block["select"].append(rewrite_cpp(b.strip()))
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block["setup"].append(("select", rewrite_cpp(b.strip())))
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continue
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if a[0] == "slice":
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m = re.match(r"^\s*slice\s+(\S+)\s+(.*?)\s*$", l)
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block["setup"].append(("slice", m.group(1), rewrite_cpp(m.group(2))))
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continue
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if a[0] == "choice":
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m = re.match(r"^\s*choice\s+<(.*?)>\s+(\S+)\s+(.*?)\s*$", l)
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block["setup"].append(("choice", m.group(1), m.group(2), rewrite_cpp(m.group(3))))
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continue
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if a[0] == "define":
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m = re.match(r"^\s*define\s+<(.*?)>\s+(\S+)\s+(.*?)\s*$", l)
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block["setup"].append(("define", m.group(1), m.group(2), rewrite_cpp(m.group(3))))
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continue
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if a[0] == "index":
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@ -242,6 +258,11 @@ def process_pmgfile(f, filename):
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block["filter"].append(rewrite_cpp(b.strip()))
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continue
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if a[0] == "set":
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m = re.match(r"^\s*set\s+(\S+)\s+(.*?)\s*$", l)
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block["sets"].append((m.group(1), rewrite_cpp(m.group(2))))
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continue
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if a[0] == "optional":
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block["optional"] = True
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continue
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@ -252,14 +273,16 @@ def process_pmgfile(f, filename):
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if a[0] == "generate":
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block["genargs"] = list([int(s) for s in a[1:]])
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if len(block["genargs"]) == 0: block["genargs"].append(100)
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if len(block["genargs"]) == 1: block["genargs"].append(0)
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assert len(block["genargs"]) == 2
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block["gencode"] = list()
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assert len(block["genargs"]) < 2
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while True:
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linenr += 1
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l = f.readline()
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assert l != ""
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a = l.split()
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if a[0] == "endmatch": break
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if len(a) == 1 and a[0] == "endmatch": break
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block["gencode"].append(rewrite_cpp(l.rstrip()))
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break
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@ -357,8 +380,17 @@ with open(outfile, "w") as f:
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index_types = list()
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for entry in block["index"]:
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index_types.append(entry[0])
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value_types = ["Cell*"]
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for entry in block["setup"]:
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if entry[0] == "slice":
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value_types.append("int")
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if entry[0] == "choice":
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value_types.append(entry[1])
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if entry[0] == "define":
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value_types.append(entry[1])
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print(" typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f)
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print(" dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
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print(" typedef std::tuple<{}> index_{}_value_type;".format(", ".join(value_types), index), file=f)
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print(" dict<index_{}_key_type, vector<index_{}_value_type>> index_{};".format(index, index, index), file=f)
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print(" dict<SigBit, pool<Cell*>> sigusers;", file=f)
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print(" pool<Cell*> blacklist_cells;", file=f)
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print(" pool<Cell*> autoremove_cells;", file=f)
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@ -457,12 +489,34 @@ with open(outfile, "w") as f:
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if block["type"] == "match":
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print(" do {", file=f)
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print(" Cell *{} = cell;".format(block["cell"]), file=f)
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for expr in block["select"]:
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print(" if (!({})) break;".format(expr), file=f)
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print(" index_{}_value_type value;".format(index), file=f)
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print(" std::get<0>(value) = cell;", file=f)
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loopcnt = 0
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valueidx = 1
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for item in block["setup"]:
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if item[0] == "select":
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print(" if (!({})) continue;".format(item[1]), file=f)
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if item[0] == "slice":
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print(" int &{} = std::get<{}>(value);".format(item[1], valueidx), file=f)
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print(" for ({} = 0; {} < {}; {}++) {{".format(item[1], item[1], item[2], item[1]), file=f)
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valueidx += 1
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loopcnt += 1
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if item[0] == "choice":
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print(" vector<{}> _pmg_choices_{} = {};".format(item[1], item[2], item[3]), file=f)
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print(" for (const {} &{} : _pmg_choices_{}) {{".format(item[1], item[2], item[2]), file=f)
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print(" std::get<{}>(value) = {};".format(valueidx, item[2]), file=f)
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valueidx += 1
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loopcnt += 1
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if item[0] == "define":
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print(" {} &{} = std::get<{}>(value);".format(item[1], item[2], valueidx), file=f)
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print(" {} = {};".format(item[2], item[3]), file=f)
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valueidx += 1
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print(" index_{}_key_type key;".format(index), file=f)
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for field, entry in enumerate(block["index"]):
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print(" std::get<{}>(key) = {};".format(field, entry[1]), file=f)
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print(" index_{}[key].push_back(cell);".format(index), file=f)
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print(" index_{}[key].push_back(value);".format(index), file=f)
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for i in range(loopcnt):
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print(" }", file=f)
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print(" } while (0);", file=f)
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print(" }", file=f)
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@ -535,6 +589,8 @@ with open(outfile, "w") as f:
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const_st.add(s)
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elif blocks[i]["type"] == "match":
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const_st.add(blocks[i]["cell"])
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for item in blocks[i]["sets"]:
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const_st.add(item[0])
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else:
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assert False
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@ -548,6 +604,10 @@ with open(outfile, "w") as f:
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s = block["cell"]
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assert s not in const_st
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nonconst_st.add(s)
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for item in block["sets"]:
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if item[0] in const_st:
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const_st.remove(item[0])
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nonconst_st.add(item[0])
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else:
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assert False
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@ -570,7 +630,7 @@ with open(outfile, "w") as f:
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print("", file=f)
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for s in sorted(restore_st):
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t = state_types[current_pattern][s]
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print(" {} backup_{} = {};".format(t, s, s), file=f)
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print(" {} _pmg_backup_{} = {};".format(t, s, s), file=f)
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if block["type"] == "code":
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print("", file=f)
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@ -610,7 +670,7 @@ with open(outfile, "w") as f:
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print("", file=f)
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for s in sorted(restore_st):
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t = state_types[current_pattern][s]
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print(" {} = backup_{};".format(s, s), file=f)
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print(" {} = _pmg_backup_{};".format(s, s), file=f)
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for s in sorted(nonconst_st):
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if s not in restore_st:
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t = state_types[current_pattern][s]
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@ -622,7 +682,7 @@ with open(outfile, "w") as f:
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elif block["type"] == "match":
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assert len(restore_st) == 0
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print(" Cell* backup_{} = {};".format(block["cell"], block["cell"]), file=f)
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print(" Cell* _pmg_backup_{} = {};".format(block["cell"], block["cell"]), file=f)
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if len(block["if"]):
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for expr in block["if"]:
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@ -630,7 +690,7 @@ with open(outfile, "w") as f:
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print(" if (!({})) {{".format(expr), file=f)
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print(" {} = nullptr;".format(block["cell"]), file=f)
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print(" block_{}(recursion+1);".format(index+1), file=f)
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print(" {} = backup_{};".format(block["cell"], block["cell"]), file=f)
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print(" {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
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print(" return;", file=f)
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print(" }", file=f)
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@ -645,21 +705,37 @@ with open(outfile, "w") as f:
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print("", file=f)
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print(" if (cells_ptr != index_{}.end()) {{".format(index), file=f)
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print(" const vector<Cell*> &cells = cells_ptr->second;".format(index), file=f)
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print(" for (int idx = 0; idx < GetSize(cells); idx++) {", file=f)
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print(" {} = cells[idx];".format(block["cell"]), file=f)
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print(" const vector<index_{}_value_type> &cells = cells_ptr->second;".format(index), file=f)
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print(" for (int _pmg_idx = 0; _pmg_idx < GetSize(cells); _pmg_idx++) {", file=f)
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print(" {} = std::get<0>(cells[_pmg_idx]);".format(block["cell"]), file=f)
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valueidx = 1
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for item in block["setup"]:
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if item[0] == "slice":
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print(" const int &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], valueidx), file=f)
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valueidx += 1
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if item[0] == "choice":
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print(" const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
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valueidx += 1
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if item[0] == "define":
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print(" const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
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valueidx += 1
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print(" if (blacklist_cells.count({})) continue;".format(block["cell"]), file=f)
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for expr in block["filter"]:
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print(" if (!({})) continue;".format(expr), file=f)
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if block["semioptional"] or block["genargs"] is not None:
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print(" found_any_match = true;", file=f)
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print(" auto rollback_ptr = rollback_cache.insert(make_pair(cells[idx], recursion));", file=f)
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for item in block["sets"]:
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print(" auto _pmg_backup_{} = {};".format(item[0], item[0]), file=f)
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print(" {} = {};".format(item[0], item[1]), file=f)
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print(" auto rollback_ptr = rollback_cache.insert(make_pair(std::get<0>(cells[_pmg_idx]), recursion));", file=f)
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print(" block_{}(recursion+1);".format(index+1), file=f)
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for item in block["sets"]:
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print(" {} = _pmg_backup_{};".format(item[0], item[0]), file=f)
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print(" if (rollback_ptr.second)", file=f)
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print(" rollback_cache.erase(rollback_ptr.first);", file=f)
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print(" if (rollback) {", file=f)
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print(" if (rollback != recursion) {{".format(index+1), file=f)
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print(" {} = backup_{};".format(block["cell"], block["cell"]), file=f)
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print(" {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
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print(" return;", file=f)
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print(" }", file=f)
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print(" rollback = 0;", file=f)
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@ -676,13 +752,11 @@ with open(outfile, "w") as f:
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if block["semioptional"]:
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print(" if (!found_any_match) block_{}(recursion+1);".format(index+1), file=f)
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print(" {} = backup_{};".format(block["cell"], block["cell"]), file=f)
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print(" {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
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if block["genargs"] is not None:
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print("#define finish do { rollback = -1; return; } while(0)", file=f)
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print(" if (generate_mode && !found_any_match) {", file=f)
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if len(block["genargs"]) == 1:
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print(" if (rng(100) >= {}) return;".format(block["genargs"][0]), file=f)
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print(" if (generate_mode && rng(100) < (found_any_match ? {} : {})) {{".format(block["genargs"][1], block["genargs"][0]), file=f)
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for line in block["gencode"]:
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print(" " + line, file=f)
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print(" }", file=f)
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@ -99,6 +99,24 @@ void reduce_tree(test_pmgen_pm &pm)
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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void opt_eqpmux(test_pmgen_pm &pm)
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{
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auto &st = pm.st_eqpmux;
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SigSpec Y = st.pmux->getPort(ID::Y);
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int width = GetSize(Y);
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SigSpec EQ = st.pmux->getPort(ID::B).extract(st.pmux_slice_eq*width, width);
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SigSpec NE = st.pmux->getPort(ID::B).extract(st.pmux_slice_ne*width, width);
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log("Found eqpmux circuit driving %s (eq=%s, ne=%s, pmux=%s).\n",
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log_signal(Y), log_id(st.eq), log_id(st.ne), log_id(st.pmux));
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pm.autoremove(st.pmux);
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Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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#define GENERATE_PATTERN(pmclass, pattern) \
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generate_pattern<pmclass>([](pmclass &pm, std::function<void()> f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design)
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@ -149,16 +167,17 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
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log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass);
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int modcnt = 0;
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int maxmodcnt = 100;
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int maxsubcnt = 4;
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int timeout = 0;
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vector<Module*> mods;
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while (modcnt < 100)
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while (modcnt < maxmodcnt)
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{
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int submodcnt = 0, itercnt = 0, cellcnt = 0;
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Module *mod = design->addModule(NEW_ID);
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while (modcnt < 100 && submodcnt < maxsubcnt && itercnt++ < 1000)
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while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000)
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{
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if (timeout++ > 10000)
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log_error("pmgen generator is stuck: 10000 iterations an no matching module generated.\n");
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@ -232,6 +251,12 @@ struct TestPmgenPass : public Pass {
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log("Demo for recursive pmgen patterns. Map trees of AND/OR/XOR to $reduce_*.\n");
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log("\n");
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log("\n");
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log(" test_pmgen -eqpmux [options] [selection]\n");
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log("\n");
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log("Demo for recursive pmgen patterns. Optimize EQ/NE/PMUX circuits.\n");
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log("\n");
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log("\n");
|
||||
log(" test_pmgen -generate [options] <pattern_name>\n");
|
||||
log("\n");
|
||||
|
|
@ -277,6 +302,25 @@ struct TestPmgenPass : public Pass {
|
|||
test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_tree);
|
||||
}
|
||||
|
||||
void execute_eqpmux(std::vector<std::string> args, RTLIL::Design *design)
|
||||
{
|
||||
log_header(design, "Executing TEST_PMGEN pass (-eqpmux).\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 2; argidx < args.size(); argidx++)
|
||||
{
|
||||
// if (args[argidx] == "-singleton") {
|
||||
// singleton_mode = true;
|
||||
// continue;
|
||||
// }
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules())
|
||||
test_pmgen_pm(module, module->selected_cells()).run_eqpmux(opt_eqpmux);
|
||||
}
|
||||
|
||||
void execute_generate(std::vector<std::string> args, RTLIL::Design *design)
|
||||
{
|
||||
log_header(design, "Executing TEST_PMGEN pass (-generate).\n");
|
||||
|
|
@ -299,6 +343,9 @@ struct TestPmgenPass : public Pass {
|
|||
if (pattern == "reduce")
|
||||
return GENERATE_PATTERN(test_pmgen_pm, reduce);
|
||||
|
||||
if (pattern == "eqpmux")
|
||||
return GENERATE_PATTERN(test_pmgen_pm, eqpmux);
|
||||
|
||||
if (pattern == "ice40_dsp")
|
||||
return GENERATE_PATTERN(ice40_dsp_pm, ice40_dsp);
|
||||
|
||||
|
|
@ -319,6 +366,8 @@ struct TestPmgenPass : public Pass {
|
|||
return execute_reduce_chain(args, design);
|
||||
if (args[1] == "-reduce_tree")
|
||||
return execute_reduce_tree(args, design);
|
||||
if (args[1] == "-eqpmux")
|
||||
return execute_eqpmux(args, design);
|
||||
if (args[1] == "-generate")
|
||||
return execute_generate(args, design);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -60,8 +60,8 @@ code portname
|
|||
endcode
|
||||
|
||||
match next
|
||||
select nusers(port(next, \Y)) == 2
|
||||
select next->type.in($_AND_, $_OR_, $_XOR_)
|
||||
select nusers(port(next, \Y)) == 2
|
||||
index <IdString> next->type === first->type
|
||||
index <SigSpec> port(next, \Y) === port(first, portname)
|
||||
endmatch
|
||||
|
|
@ -77,8 +77,8 @@ arg first
|
|||
|
||||
match next
|
||||
semioptional
|
||||
select nusers(port(next, \Y)) == 2
|
||||
select next->type.in($_AND_, $_OR_, $_XOR_)
|
||||
select nusers(port(next, \Y)) == 2
|
||||
index <IdString> next->type === chain.back().first->type
|
||||
index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
|
||||
generate 10
|
||||
|
|
@ -104,3 +104,86 @@ finally
|
|||
if (next)
|
||||
chain.pop_back();
|
||||
endcode
|
||||
|
||||
// ==================================================================
|
||||
|
||||
pattern eqpmux
|
||||
|
||||
state <bool> eq_ne_signed
|
||||
state <SigSpec> eq_inA eq_inB
|
||||
state <int> pmux_slice_eq pmux_slice_ne
|
||||
|
||||
match eq
|
||||
select eq->type == $eq
|
||||
choice <IdString> AB {\A, \B}
|
||||
define <IdString> BA AB == \A ? \B : \A
|
||||
set eq_inA port(eq, \A)
|
||||
set eq_inB port(eq, \B)
|
||||
set eq_ne_signed param(eq, \A_SIGNED).as_bool()
|
||||
generate 100 10
|
||||
SigSpec A = module->addWire(NEW_ID, rng(7)+1);
|
||||
SigSpec B = module->addWire(NEW_ID, rng(7)+1);
|
||||
SigSpec Y = module->addWire(NEW_ID);
|
||||
module->addEq(NEW_ID, A, B, Y, rng(2));
|
||||
endmatch
|
||||
|
||||
match pmux
|
||||
select pmux->type == $pmux
|
||||
slice idx GetSize(port(pmux, \S))
|
||||
index <SigBit> port(pmux, \S)[idx] === port(eq, \Y)
|
||||
set pmux_slice_eq idx
|
||||
generate 100 10
|
||||
int width = rng(7) + 1;
|
||||
int numsel = rng(4) + 1;
|
||||
int idx = rng(numsel);
|
||||
|
||||
SigSpec A = module->addWire(NEW_ID, width);
|
||||
SigSpec Y = module->addWire(NEW_ID, width);
|
||||
|
||||
SigSpec B, S;
|
||||
for (int i = 0; i < numsel; i++) {
|
||||
B.append(module->addWire(NEW_ID, width));
|
||||
S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID));
|
||||
}
|
||||
|
||||
module->addPmux(NEW_ID, A, B, S, Y);
|
||||
endmatch
|
||||
|
||||
match ne
|
||||
select ne->type == $ne
|
||||
choice <IdString> AB {\A, \B}
|
||||
define <IdString> BA (AB == \A ? \B : \A)
|
||||
index <SigSpec> port(ne, AB) === eq_inA
|
||||
index <SigSpec> port(ne, BA) === eq_inB
|
||||
index <int> param(ne, \A_SIGNED).as_bool() === eq_ne_signed
|
||||
generate 100 10
|
||||
SigSpec A = eq_inA, B = eq_inB, Y;
|
||||
if (rng(2)) {
|
||||
std::swap(A, B);
|
||||
}
|
||||
if (rng(2)) {
|
||||
for (auto bit : port(pmux, \S)) {
|
||||
if (nusers(bit) < 2)
|
||||
Y.append(bit);
|
||||
}
|
||||
if (GetSize(Y))
|
||||
Y = Y[rng(GetSize(Y))];
|
||||
else
|
||||
Y = module->addWire(NEW_ID);
|
||||
} else {
|
||||
Y = module->addWire(NEW_ID);
|
||||
}
|
||||
module->addNe(NEW_ID, A, B, Y, rng(2));
|
||||
endmatch
|
||||
|
||||
match pmux2
|
||||
select pmux2->type == $pmux
|
||||
slice idx GetSize(port(pmux2, \S))
|
||||
index <Cell*> pmux2 === pmux
|
||||
index <SigBit> port(pmux2, \S)[idx] === port(ne, \Y)
|
||||
set pmux_slice_ne idx
|
||||
endmatch
|
||||
|
||||
code
|
||||
accept;
|
||||
endcode
|
||||
|
|
|
|||
Loading…
Reference in New Issue