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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)

This commit is contained in:
Clifford Wolf 2013-11-02 21:13:01 +01:00
parent f912e029de
commit ada80545fa
3 changed files with 12 additions and 8 deletions
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2
frontends/ast/genrtlil.cc
View File

@ -570,6 +570,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
this_width = range->range_left - range->range_right + 1;
} else
width_hint = std::max(width_hint, this_width);
if (!id2ast->is_signed)
sign_hint = false;
break;
case AST_TO_SIGNED:

6
frontends/ast/simplify.cc
View File

@ -920,8 +920,10 @@ skip_dynamic_range_lvalue_expansion:;
if (0) { case AST_POS: const_func = RTLIL::const_pos; }
if (0) { case AST_NEG: const_func = RTLIL::const_neg; }
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint), dummy_arg, sign_hint, false, width_hint);
newNode = mkconst_bits(y.bits, sign_hint);
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1);
newNode = mkconst_bits(y.bits, children[0]->is_signed);
// RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint), dummy_arg, sign_hint, false, width_hint);
// newNode = mkconst_bits(y.bits, sign_hint);
}
break;
case AST_TERNARY:

12
tests/simple/vloghammer.v
View File

@ -73,10 +73,10 @@ module test10(a, b, c, y);
assign y = ^(a ? b : c);
endmodule
module test11(a, b, y);
input signed [3:0] a;
input signed [3:0] b;
output signed [5:0] y;
assign y = -(5'd27);
endmodule
// module test11(a, b, y);
// input signed [3:0] a;
// input signed [3:0] b;
// output signed [5:0] y;
// assign y = -(5'd27);
// endmodule