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326
manual/literature.bib
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@ -1,163 +1,163 @@
@inproceedings{intersynth, @inproceedings{intersynth,
title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic}, title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},
author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm}, author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},
booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages}, booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},
pages={194--201}, pages={194--201},
year={2012} year={2012}
} }
@incollection{intersynthFdlBookChapter, @incollection{intersynthFdlBookChapter,
title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures}, title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},
author={Johann Glaser and Clifford Wolf}, author={Johann Glaser and Clifford Wolf},
booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12}, booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12},
editor={Jan Haase}, editor={Jan Haase},
publisher={Springer}, publisher={Springer},
year={2013}, year={2013},
note={to appear} note={to appear}
} }
@unpublished{BACC, @unpublished{BACC,
author = {Clifford Wolf}, author = {Clifford Wolf},
title = {Design and Implementation of the Yosys Open SYnthesis Suite}, title = {Design and Implementation of the Yosys Open SYnthesis Suite},
note = {Bachelor Thesis, Vienna University of Technology}, note = {Bachelor Thesis, Vienna University of Technology},
year = {2013} year = {2013}
} }
@unpublished{VerilogFossEval, @unpublished{VerilogFossEval,
author = {Clifford Wolf}, author = {Clifford Wolf},
title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility}, title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility},
note = {Unpublished Student Research Paper, Vienna University of Technology}, note = {Unpublished Student Research Paper, Vienna University of Technology},
year = {2012} year = {2012}
} }
@article{ABEL, @article{ABEL,
title={A High-Level Design Language for Programmable Logic Devices}, title={A High-Level Design Language for Programmable Logic Devices},
author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright}, author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright},
journal={VLSI Design (Manhasset NY: CPM Publications)}, journal={VLSI Design (Manhasset NY: CPM Publications)},
year={June 1985}, year={June 1985},
pages={50-62} pages={50-62}
} }
@MISC{Cheng93vl2mv:a, @MISC{Cheng93vl2mv:a,
author = {S-T Cheng and G York and R K Brayton}, author = {S-T Cheng and G York and R K Brayton},
title = {VL2MV: A Compiler from Verilog to BLIF-MV}, title = {VL2MV: A Compiler from Verilog to BLIF-MV},
year = {1993} year = {1993}
} }
@MISC{Odin, @MISC{Odin,
author = {Peter Jamieson and Jonathan Rose}, author = {Peter Jamieson and Jonathan Rose},
title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS}, title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS},
year = {2005} year = {2005}
} }
@inproceedings{vtr2012, @inproceedings{vtr2012,
title={The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing}, title={The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing},
author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson}, author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
booktitle={Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays}, booktitle={Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
pages={77--86}, pages={77--86},
year={2012}, year={2012},
organization={ACM} organization={ACM}
} }
@MISC{LogicSynthesis, @MISC{LogicSynthesis,
author = {G D Hachtel and F Somenzi}, author = {G D Hachtel and F Somenzi},
title = {Logic Synthesis and Verification Algorithms}, title = {Logic Synthesis and Verification Algorithms},
year = {1996} year = {1996}
} }
@ARTICLE{Verilog2005, @ARTICLE{Verilog2005,
journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)}, journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
title={IEEE Standard for Verilog Hardware Description Language}, title={IEEE Standard for Verilog Hardware Description Language},
year={2006}, year={2006},
doi={10.1109/IEEESTD.2006.99495} doi={10.1109/IEEESTD.2006.99495}
} }
@ARTICLE{VerilogSynth, @ARTICLE{VerilogSynth,
journal={IEEE Std 1364.1-2002}, journal={IEEE Std 1364.1-2002},
title={IEEE Standard for Verilog Register Transfer Level Synthesis}, title={IEEE Standard for Verilog Register Transfer Level Synthesis},
year={2002}, year={2002},
doi={10.1109/IEEESTD.2002.94220} doi={10.1109/IEEESTD.2002.94220}
} }
@ARTICLE{VHDL, @ARTICLE{VHDL,
journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual}, journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual},
year={2009}, year={2009},
month={26}, month={26},
doi={10.1109/IEEESTD.2009.4772740} doi={10.1109/IEEESTD.2009.4772740}
} }
@ARTICLE{VHDLSynth, @ARTICLE{VHDLSynth,
journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis}, journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},
year={2004}, year={2004},
doi={10.1109/IEEESTD.2004.94802} doi={10.1109/IEEESTD.2004.94802}
} }
@ARTICLE{IP-XACT, @ARTICLE{IP-XACT,
journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows},
year={2010}, year={2010},
pages={C1-360}, pages={C1-360},
keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema},
doi={10.1109/IEEESTD.2010.5417309},} doi={10.1109/IEEESTD.2010.5417309},}
@book{Dragonbook, @book{Dragonbook,
author = {Aho, Alfred V. and Sethi, Ravi and Ullman, Jeffrey D.}, author = {Aho, Alfred V. and Sethi, Ravi and Ullman, Jeffrey D.},
title = {Compilers: principles, techniques, and tools}, title = {Compilers: principles, techniques, and tools},
year = {1986}, year = {1986},
isbn = {0-201-10088-6}, isbn = {0-201-10088-6},
publisher = {Addison-Wesley Longman Publishing Co., Inc.}, publisher = {Addison-Wesley Longman Publishing Co., Inc.},
address = {Boston, MA, USA}, address = {Boston, MA, USA},
} }
@INPROCEEDINGS{Cummings00, @INPROCEEDINGS{Cummings00,
author = {Clifford E. Cummings and Sunburst Design Inc}, author = {Clifford E. Cummings and Sunburst Design Inc},
title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}, title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill},
booktitle = {SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper}, booktitle = {SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper},
year = {2000} year = {2000}
} }
@ARTICLE{MURPHY, @ARTICLE{MURPHY,
author={D. L. Klipstein}, author={D. L. Klipstein},
journal={Cahners Publishing Co., EEE Magazine, Vol. 15, No. 8}, journal={Cahners Publishing Co., EEE Magazine, Vol. 15, No. 8},
title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects}, title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects},
year={August 1967} year={August 1967}
} }
@INPROCEEDINGS{fsmextract, @INPROCEEDINGS{fsmextract,
author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren},
booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, title={A highly efficient method for extracting FSMs from flattened gate-level netlist},
year={2010}, year={2010},
pages={2610-2613}, pages={2610-2613},
keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing},
doi={10.1109/ISCAS.2010.5537093},} doi={10.1109/ISCAS.2010.5537093},}
@ARTICLE{MultiLevelLogicSynth, @ARTICLE{MultiLevelLogicSynth,
author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.},
journal={Proceedings of the IEEE}, journal={Proceedings of the IEEE},
title={Multilevel logic synthesis}, title={Multilevel logic synthesis},
year={1990}, year={1990},
volume={78}, volume={78},
number={2}, number={2},
pages={264-300}, pages={264-300},
keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon},
doi={10.1109/5.52213}, doi={10.1109/5.52213},
ISSN={0018-9219},} ISSN={0018-9219},}
@article{UllmannSubgraphIsomorphism, @article{UllmannSubgraphIsomorphism,
author = {Ullmann, J. R.}, author = {Ullmann, J. R.},
title = {An Algorithm for Subgraph Isomorphism}, title = {An Algorithm for Subgraph Isomorphism},
journal = {J. ACM}, journal = {J. ACM},
issue_date = {Jan. 1976}, issue_date = {Jan. 1976},
volume = {23}, volume = {23},
number = {1}, number = {1},
month = jan, month = jan,
year = {1976}, year = {1976},
issn = {0004-5411}, issn = {0004-5411},
pages = {31--42}, pages = {31--42},
numpages = {12}, numpages = {12},
doi = {10.1145/321921.321925}, doi = {10.1145/321921.321925},
acmid = {321925}, acmid = {321925},
publisher = {ACM}, publisher = {ACM},
address = {New York, NY, USA}, address = {New York, NY, USA},
} }

268
manual/weblinks.bib
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@ -1,134 +1,134 @@
@misc{YosysGit, @misc{YosysGit,
author = {Clifford Wolf}, author = {Clifford Wolf},
title = {{Yosys Open SYnthesis Suite (YOSYS)}}, title = {{Yosys Open SYnthesis Suite (YOSYS)}},
note = {\url{http://github.com/cliffordwolf/yosys}} note = {\url{http://github.com/cliffordwolf/yosys}}
} }
@misc{YosysTestsGit, @misc{YosysTestsGit,
author = {Clifford Wolf}, author = {Clifford Wolf},
title = {{Yosys Test Bench}}, title = {{Yosys Test Bench}},
note = {\url{http://github.com/cliffordwolf/yosys-tests}} note = {\url{http://github.com/cliffordwolf/yosys-tests}}
} }
@misc{VlogHammer, @misc{VlogHammer,
author = {Clifford Wolf}, author = {Clifford Wolf},
title = {{VlogHammer Verilog Synthesis Regression Tests}}, title = {{VlogHammer Verilog Synthesis Regression Tests}},
note = {\url{http://github.com/cliffordwolf/VlogHammer}} note = {\url{http://github.com/cliffordwolf/VlogHammer}}
} }
@misc{Icarus, @misc{Icarus,
author = {Stephen Williams}, author = {Stephen Williams},
title = {{Icarus Verilog}}, title = {{Icarus Verilog}},
note = {Version 0.8.7, \url{http://iverilog.icarus.com/}} note = {Version 0.8.7, \url{http://iverilog.icarus.com/}}
} }
@misc{VTR, @misc{VTR,
author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson}, author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
title = {{The Verilog-to-Routing (VTR) Project for FPGAs}}, title = {{The Verilog-to-Routing (VTR) Project for FPGAs}},
note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}} note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}
} }
@misc{HANA, @misc{HANA,
author = {Parvez Ahmad}, author = {Parvez Ahmad},
title = {{HDL Analyzer and Netlist Architect (HANA)}}, title = {{HDL Analyzer and Netlist Architect (HANA)}},
note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}} note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}
} }
@misc{MVSIS, @misc{MVSIS,
author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design}, author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},
title = {{MVSIS: Logic Synthesis and Verification}}, title = {{MVSIS: Logic Synthesis and Verification}},
note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}} note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}
} }
@misc{VIS, @misc{VIS,
author = {{The VIS group}}, author = {{The VIS group}},
title = {{VIS: A system for Verification and Synthesis}}, title = {{VIS: A system for Verification and Synthesis}},
note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}} note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}
} }
@misc{ABC, @misc{ABC,
author = {{Berkeley Logic Synthesis and Verification Group}}, author = {{Berkeley Logic Synthesis and Verification Group}},
title = {{ABC: A System for Sequential Synthesis and Verification}}, title = {{ABC: A System for Sequential Synthesis and Verification}},
note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}} note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}
} }
@misc{AIGER, @misc{AIGER,
author = {{Armin Biere, Johannes Kepler University Linz, Austria}}, author = {{Armin Biere, Johannes Kepler University Linz, Austria}},
title = {{AIGER}}, title = {{AIGER}},
note = {\url{http://fmv.jku.at/aiger/}} note = {\url{http://fmv.jku.at/aiger/}}
} }
@misc{XilinxWebPACK, @misc{XilinxWebPACK,
author = {{Xilinx, Inc.}}, author = {{Xilinx, Inc.}},
title = {{ISE WebPACK Design Software}}, title = {{ISE WebPACK Design Software}},
note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}} note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}
} }
@misc{QuartusWeb, @misc{QuartusWeb,
author = {{Altera, Inc.}}, author = {{Altera, Inc.}},
title = {{Quartus II Web Edition Software}}, title = {{Quartus II Web Edition Software}},
note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}} note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}
} }
@misc{OR1200, @misc{OR1200,
title = {{OpenRISC 1200 CPU}}, title = {{OpenRISC 1200 CPU}},
note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}} note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}
} }
@misc{openMSP430, @misc{openMSP430,
title = {{openMSP430 CPU}}, title = {{openMSP430 CPU}},
note = {\url{http://opencores.org/project,openmsp430}} note = {\url{http://opencores.org/project,openmsp430}}
} }
@misc{i2cmaster, @misc{i2cmaster,
title = {{OpenCores I$^2$C Core}}, title = {{OpenCores I$^2$C Core}},
note = {\url{http://opencores.org/project,i2c}} note = {\url{http://opencores.org/project,i2c}}
} }
@misc{k68, @misc{k68,
title = {{OpenCores k68 Core}}, title = {{OpenCores k68 Core}},
note = {\url{http://opencores.org/project,k68}} note = {\url{http://opencores.org/project,k68}}
} }
@misc{bison, @misc{bison,
title = {{GNU Bison}}, title = {{GNU Bison}},
note = {\url{http://www.gnu.org/software/bison/}} note = {\url{http://www.gnu.org/software/bison/}}
} }
@misc{flex, @misc{flex,
title = {{Flex}}, title = {{Flex}},
note = {\url{http://flex.sourceforge.net/}} note = {\url{http://flex.sourceforge.net/}}
} }
@misc{C_to_Verilog, @misc{C_to_Verilog,
title = {{C-to-Verilog}}, title = {{C-to-Verilog}},
note = {\url{http://www.c-to-verilog.com/}} note = {\url{http://www.c-to-verilog.com/}}
} }
@misc{LegUp, @misc{LegUp,
title = {{LegUp}}, title = {{LegUp}},
note = {\url{http://legup.eecg.utoronto.ca/}} note = {\url{http://legup.eecg.utoronto.ca/}}
} }
@misc{LibertyFormat, @misc{LibertyFormat,
title = {{The Liberty Library Modeling Standard}}, title = {{The Liberty Library Modeling Standard}},
note = {\url{http://www.opensourceliberty.org/}} note = {\url{http://www.opensourceliberty.org/}}
} }
@misc{ASIC-WORLD, @misc{ASIC-WORLD,
title = {{World of ASIC}}, title = {{World of ASIC}},
note = {\url{http://www.asic-world.com/}} note = {\url{http://www.asic-world.com/}}
} }
@misc{Formality, @misc{Formality,
title = {{Synopsys Formality Equivalence Checking}}, title = {{Synopsys Formality Equivalence Checking}},
note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}}, note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},
} }
@misc{bigint, @misc{bigint,
author = {Matt McCutchen}, author = {Matt McCutchen},
title = {{C++ Big Integer Library}}, title = {{C++ Big Integer Library}},
note = {\url{http://mattmccutchen.net/bigint/}} note = {\url{http://mattmccutchen.net/bigint/}}
} }

246
tests/asicworld/code_hdl_models_arbiter.v
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@ -1,123 +1,123 @@
//---------------------------------------------------- //----------------------------------------------------
// A four level, round-robin arbiter. This was // A four level, round-robin arbiter. This was
// orginally coded by WD Peterson in VHDL. // orginally coded by WD Peterson in VHDL.
//---------------------------------------------------- //----------------------------------------------------
module arbiter ( module arbiter (
clk, clk,
rst, rst,
req3, req3,
req2, req2,
req1, req1,
req0, req0,
gnt3, gnt3,
gnt2, gnt2,
gnt1, gnt1,
gnt0 gnt0
); );
// --------------Port Declaration----------------------- // --------------Port Declaration-----------------------
input clk; input clk;
input rst; input rst;
input req3; input req3;
input req2; input req2;
input req1; input req1;
input req0; input req0;
output gnt3; output gnt3;
output gnt2; output gnt2;
output gnt1; output gnt1;
output gnt0; output gnt0;
//--------------Internal Registers---------------------- //--------------Internal Registers----------------------
wire [1:0] gnt ; wire [1:0] gnt ;
wire comreq ; wire comreq ;
wire beg ; wire beg ;
wire [1:0] lgnt ; wire [1:0] lgnt ;
wire lcomreq ; wire lcomreq ;
reg lgnt0 ; reg lgnt0 ;
reg lgnt1 ; reg lgnt1 ;
reg lgnt2 ; reg lgnt2 ;
reg lgnt3 ; reg lgnt3 ;
reg lasmask ; reg lasmask ;
reg lmask0 ; reg lmask0 ;
reg lmask1 ; reg lmask1 ;
reg ledge ; reg ledge ;
//--------------Code Starts Here----------------------- //--------------Code Starts Here-----------------------
always @ (posedge clk) always @ (posedge clk)
if (rst) begin if (rst) begin
lgnt0 <= 0; lgnt0 <= 0;
lgnt1 <= 0; lgnt1 <= 0;
lgnt2 <= 0; lgnt2 <= 0;
lgnt3 <= 0; lgnt3 <= 0;
end else begin end else begin
lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0) lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0) | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0) | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
| (~lcomreq & lmask1 & lmask0 & req0 ) | (~lcomreq & lmask1 & lmask0 & req0 )
| ( lcomreq & lgnt0 ); | ( lcomreq & lgnt0 );
lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1) lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0) | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0) | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req1 & ~req0) | (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
| ( lcomreq & lgnt1); | ( lcomreq & lgnt1);
lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1) lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req2) | (~lcomreq & ~lmask1 & lmask0 & req2)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0) | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0) | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
| ( lcomreq & lgnt2); | ( lcomreq & lgnt2);
lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1) lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2) | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
| (~lcomreq & lmask1 & ~lmask0 & req3) | (~lcomreq & lmask1 & ~lmask0 & req3)
| (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0) | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
| ( lcomreq & lgnt3); | ( lcomreq & lgnt3);
end end
//---------------------------------------------------- //----------------------------------------------------
// lasmask state machine. // lasmask state machine.
//---------------------------------------------------- //----------------------------------------------------
assign beg = (req3 | req2 | req1 | req0) & ~lcomreq; assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
always @ (posedge clk) always @ (posedge clk)
begin begin
lasmask <= (beg & ~ledge & ~lasmask); lasmask <= (beg & ~ledge & ~lasmask);
ledge <= (beg & ~ledge & lasmask) ledge <= (beg & ~ledge & lasmask)
| (beg & ledge & ~lasmask); | (beg & ledge & ~lasmask);
end end
//---------------------------------------------------- //----------------------------------------------------
// comreq logic. // comreq logic.
//---------------------------------------------------- //----------------------------------------------------
assign lcomreq = ( req3 & lgnt3 ) assign lcomreq = ( req3 & lgnt3 )
| ( req2 & lgnt2 ) | ( req2 & lgnt2 )
| ( req1 & lgnt1 ) | ( req1 & lgnt1 )
| ( req0 & lgnt0 ); | ( req0 & lgnt0 );
//---------------------------------------------------- //----------------------------------------------------
// Encoder logic. // Encoder logic.
//---------------------------------------------------- //----------------------------------------------------
assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)}; assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
//---------------------------------------------------- //----------------------------------------------------
// lmask register. // lmask register.
//---------------------------------------------------- //----------------------------------------------------
always @ (posedge clk ) always @ (posedge clk )
if( rst ) begin if( rst ) begin
lmask1 <= 0; lmask1 <= 0;
lmask0 <= 0; lmask0 <= 0;
end else if(lasmask) begin end else if(lasmask) begin
lmask1 <= lgnt[1]; lmask1 <= lgnt[1];
lmask0 <= lgnt[0]; lmask0 <= lgnt[0];
end else begin end else begin
lmask1 <= lmask1; lmask1 <= lmask1;
lmask0 <= lmask0; lmask0 <= lmask0;
end end
assign comreq = lcomreq; assign comreq = lcomreq;
assign gnt = lgnt; assign gnt = lgnt;
//---------------------------------------------------- //----------------------------------------------------
// Drive the outputs // Drive the outputs
//---------------------------------------------------- //----------------------------------------------------
assign gnt3 = lgnt3; assign gnt3 = lgnt3;
assign gnt2 = lgnt2; assign gnt2 = lgnt2;
assign gnt1 = lgnt1; assign gnt1 = lgnt1;
assign gnt0 = lgnt0; assign gnt0 = lgnt0;
endmodule endmodule

22
tests/asicworld/code_hdl_models_t_gate_switch.v
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@ -1,11 +1,11 @@
module t_gate_switch (L,R,nC,C); module t_gate_switch (L,R,nC,C);
inout L; inout L;
inout R; inout R;
input nC; input nC;
input C; input C;
//Syntax: keyword unique_name (drain. source, gate); //Syntax: keyword unique_name (drain. source, gate);
pmos p1 (L,R,nC); pmos p1 (L,R,nC);
nmos p2 (L,R,C); nmos p2 (L,R,C);
endmodule endmodule

38
tests/asicworld/code_verilog_tutorial_counter.v
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@ -1,19 +1,19 @@
//----------------------------------------------------- //-----------------------------------------------------
// Design Name : counter // Design Name : counter
// File Name : counter.v // File Name : counter.v
// Function : 4 bit up counter // Function : 4 bit up counter
// Coder : Deepak // Coder : Deepak
//----------------------------------------------------- //-----------------------------------------------------
module counter (clk, reset, enable, count); module counter (clk, reset, enable, count);
input clk, reset, enable; input clk, reset, enable;
output [3:0] count; output [3:0] count;
reg [3:0] count; reg [3:0] count;
always @ (posedge clk) always @ (posedge clk)
if (reset == 1'b1) begin if (reset == 1'b1) begin
count <= 0; count <= 0;
end else if ( enable == 1'b1) begin end else if ( enable == 1'b1) begin
count <= count + 1; count <= count + 1;
end end
endmodule endmodule

226
tests/asicworld/code_verilog_tutorial_counter_tb.v
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@ -1,113 +1,113 @@
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// MODULE : counter_tb // // MODULE : counter_tb //
// TOP MODULE : -- // // TOP MODULE : -- //
// // // //
// PURPOSE : 4-bit up counter test bench // // PURPOSE : 4-bit up counter test bench //
// // // //
// DESIGNER : Deepak Kumar Tala // // DESIGNER : Deepak Kumar Tala //
// // // //
// Revision History // // Revision History //
// // // //
// DEVELOPMENT HISTORY : // // DEVELOPMENT HISTORY : //
// Rev0.0 : Jan 03, 2003 // // Rev0.0 : Jan 03, 2003 //
// Initial Revision // // Initial Revision //
// // // //
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
module testbench; module testbench;
reg clk, reset, enable; reg clk, reset, enable;
wire [3:0] count; wire [3:0] count;
reg dut_error; reg dut_error;
counter U0 ( counter U0 (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.enable (enable), .enable (enable),
.count (count) .count (count)
); );
event reset_enable; event reset_enable;
event terminate_sim; event terminate_sim;
initial initial
begin begin
$display ("###################################################"); $display ("###################################################");
clk = 0; clk = 0;
reset = 0; reset = 0;
enable = 0; enable = 0;
dut_error = 0; dut_error = 0;
end end
always always
#5 clk = !clk; #5 clk = !clk;
initial initial
begin begin
$dumpfile ("counter.vcd"); $dumpfile ("counter.vcd");
$dumpvars; $dumpvars;
end end
initial initial
@ (terminate_sim) begin @ (terminate_sim) begin
$display ("Terminating simulation"); $display ("Terminating simulation");
if (dut_error == 0) begin if (dut_error == 0) begin
$display ("Simulation Result : PASSED"); $display ("Simulation Result : PASSED");
end end
else begin else begin
$display ("Simulation Result : FAILED"); $display ("Simulation Result : FAILED");
end end
$display ("###################################################"); $display ("###################################################");
#1 $finish; #1 $finish;
end end
event reset_done; event reset_done;
initial initial
forever begin forever begin
@ (reset_enable); @ (reset_enable);
@ (negedge clk) @ (negedge clk)
$display ("Applying reset"); $display ("Applying reset");
reset = 1; reset = 1;
@ (negedge clk) @ (negedge clk)
reset = 0; reset = 0;
$display ("Came out of Reset"); $display ("Came out of Reset");
-> reset_done; -> reset_done;
end end
initial begin initial begin
#10 -> reset_enable; #10 -> reset_enable;
@ (reset_done); @ (reset_done);
@ (negedge clk); @ (negedge clk);
enable = 1; enable = 1;
repeat (5) repeat (5)
begin begin
@ (negedge clk); @ (negedge clk);
end end
enable = 0; enable = 0;
#5 -> terminate_sim; #5 -> terminate_sim;
end end
reg [3:0] count_compare; reg [3:0] count_compare;
always @ (posedge clk) always @ (posedge clk)
if (reset == 1'b1) if (reset == 1'b1)
count_compare <= 0; count_compare <= 0;
else if ( enable == 1'b1) else if ( enable == 1'b1)
count_compare <= count_compare + 1; count_compare <= count_compare + 1;
always @ (negedge clk) always @ (negedge clk)
if (count_compare != count) begin if (count_compare != count) begin
$display ("DUT ERROR AT TIME%d",$time); $display ("DUT ERROR AT TIME%d",$time);
$display ("Expected value %d, Got Value %d", count_compare, count); $display ("Expected value %d, Got Value %d", count_compare, count);
dut_error = 1; dut_error = 1;
#5 -> terminate_sim; #5 -> terminate_sim;
end end
endmodule endmodule