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Fix different abc9 test

This commit is contained in:
Eddie Hung 2019-06-20 19:31:22 -07:00
parent 9faeba7a66
commit ad36eb24c0
1 changed files with 3 additions and 2 deletions
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5
backends/aiger/xaiger.cc
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@ -406,13 +406,14 @@ struct XAigerWriter
} }
for (auto bit : input_bits) { for (auto bit : input_bits) {
if (!output_bits.count(bit))
continue;
RTLIL::Wire *wire = bit.wire; RTLIL::Wire *wire = bit.wire;
// If encountering an inout port, or a keep-ed wire, then create a new wire // If encountering an inout port, or a keep-ed wire, then create a new wire
// with $inout.out suffix, make it a PO driven by the existing inout, and // with $inout.out suffix, make it a PO driven by the existing inout, and
// inherit existing inout's drivers // inherit existing inout's drivers
if ((wire->port_input && wire->port_output && output_bits.count(bit) && !undriven_bits.count(bit)) if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
|| wire->attributes.count("\\keep")) { || wire->attributes.count("\\keep")) {
log_assert(output_bits.count(bit));
RTLIL::IdString wire_name = wire->name.str() + "$inout.out"; RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
RTLIL::Wire *new_wire = module->wire(wire_name); RTLIL::Wire *new_wire = module->wire(wire_name);
if (!new_wire) if (!new_wire)