mirror of https://github.com/YosysHQ/yosys.git
sim: Fix cosimulation with nested modules having unconnected inputs
When assigning values to input ports of nested modules in cosimulation, sim needs to find the actual driver of the signal to perform the assignment. The existing code didn't handle unconnected inputs in that scenario.
This commit is contained in:
parent
e6f3914800
commit
ad2b04d63a
|
@ -223,7 +223,8 @@ struct SimInstance
|
||||||
|
|
||||||
if (wire->port_input && instance != nullptr && parent != nullptr) {
|
if (wire->port_input && instance != nullptr && parent != nullptr) {
|
||||||
for (int i = 0; i < GetSize(sig); i++) {
|
for (int i = 0; i < GetSize(sig); i++) {
|
||||||
in_parent_drivers.emplace(sig[i], parent->sigmap(instance->getPort(wire->name)[i]));
|
if (instance->hasPort(wire->name))
|
||||||
|
in_parent_drivers.emplace(sig[i], parent->sigmap(instance->getPort(wire->name)[i]));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue