mirror of https://github.com/YosysHQ/yosys.git
Continued work on counter extraction. Can recognize compatible RTL counters but not replace with hard macros.
This commit is contained in:
Andrew Zonenberg
parent
d16d05e415
commit
ad19e0c64a
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@ -25,9 +25,9 @@ USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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//get the list of cells hooked up to at least one bit of a given net
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std::set<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src)
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pool<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src)
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{
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std::set<Cell*> rval;
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pool<Cell*> rval;
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for(auto b : port)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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@ -41,8 +41,16 @@ std::set<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cel
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return rval;
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}
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//return true if there is a full-width bus connection between the two named module/port combos
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bool is_full_bus(const RTLIL::SigSpec& sig, ModIndex& index, Cell* a, RTLIL::IdString ap, Cell* b, RTLIL::IdString bp)
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//return true if there is a full-width bus connection from cell a port ap to cell b port bp
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//if other_conns_allowed is false, then we require a strict point to point connection (no other links)
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bool is_full_bus(
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const RTLIL::SigSpec& sig,
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ModIndex& index,
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Cell* a,
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RTLIL::IdString ap,
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Cell* b,
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RTLIL::IdString bp,
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bool other_conns_allowed = false)
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{
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for(auto s : sig)
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{
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@ -55,7 +63,7 @@ bool is_full_bus(const RTLIL::SigSpec& sig, ModIndex& index, Cell* a, RTLIL::IdS
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found_a = true;
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else if( (x.cell == b) && (x.port == bp) )
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found_b = true;
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else
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else if(!other_conns_allowed)
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return false;
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}
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@ -79,108 +87,149 @@ bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
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return true;
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}
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void counters_worker(SigMap &sigmap, Module *module, Cell *cell)
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void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned int& total_counters)
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{
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if (cell->type == "$alu")
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{
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//GreenPak does not support counters larger than 14 bits so immediately skip anything bigger
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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if(a_width > 14)
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return;
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//Second input must be a single bit
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int b_width = cell->getParam("\\B_WIDTH").as_int();
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if(b_width != 1)
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return;
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//Both inputs must be unsigned, so don't extract anything with a signed input
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bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
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bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
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if(a_sign || b_sign)
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return;
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//To be a counter, one input of the ALU must be a constant 1
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//TODO: can A or B be swapped in synthesized RTL or is B always the 1?
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const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
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if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
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return;
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//BI and CI must be constant 1 as well
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const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
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if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
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return;
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const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
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if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
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return;
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//Index the module
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ModIndex index(module);
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//We found a decrementer. Not sure if it's a counter yet but log for debugging
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log(" Found candidate counter %s (width %d)\n", cell->name.c_str(), a_width);
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//CO and X must be unconnected (exactly one connection to each port)
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if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
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return;
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if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
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return;
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//Y must have exactly one connection, and it has to be a $mux cell.
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//We must have a direct bus connection from our Y to their A.
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const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
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std::set<Cell*> y_loads = get_other_cells(aluy, index, cell);
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if(y_loads.size() != 1)
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return;
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Cell* count_mux = *y_loads.begin();
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if(count_mux->type != "$mux")
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return;
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if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
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return;
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//B connection of the mux is our overflow value
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const RTLIL::SigSpec overflow = sigmap(count_mux->getPort("\\B"));
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if(!overflow.is_fully_const())
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return;
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int count_value = overflow.as_int();
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//TODO: S connection of the mux must come from an inverter
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//Y connection of the mux must have exactly one load, the counter's internal register
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const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
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std::set<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
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if(muxy_loads.size() != 1)
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return;
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Cell* count_reg = *muxy_loads.begin();
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if(count_reg->type != "$dff") //TODO: support dffr/dffs?
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return;
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if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
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return;
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log(" Looks like a counter so far (count value = %d, count_reg = %s)\n",
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count_value, count_reg->name.c_str());
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/*
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log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell));
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if (GetSize(setctrl) == 1) {
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cell->setPort("\\ARST", setctrl);
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cell->setParam("\\ARST_POLARITY", setpol);
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} else {
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cell->setPort("\\ARST", clrctrl);
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cell->setParam("\\ARST_POLARITY", clrpol);
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}
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cell->type = "$adff";
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cell->unsetPort("\\SET");
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cell->unsetPort("\\CLR");
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cell->setParam("\\ARST_VALUE", reset_val);
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cell->unsetParam("\\SET_POLARITY");
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cell->unsetParam("\\CLR_POLARITY");
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SigMap& sigmap = index.sigmap;
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//Core of the counter must be an ALU
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if (cell->type != "$alu")
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return;
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*/
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//GreenPak does not support counters larger than 14 bits so immediately skip anything bigger
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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if(a_width > 14)
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return;
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//Second input must be a single bit
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int b_width = cell->getParam("\\B_WIDTH").as_int();
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if(b_width != 1)
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return;
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//Both inputs must be unsigned, so don't extract anything with a signed input
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bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
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bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
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if(a_sign || b_sign)
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return;
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//To be a counter, one input of the ALU must be a constant 1
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//TODO: can A or B be swapped in synthesized RTL or is B always the 1?
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const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
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if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
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return;
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//BI and CI must be constant 1 as well
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const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
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if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
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return;
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const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
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if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
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return;
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//CO and X must be unconnected (exactly one connection to each port)
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if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
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return;
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if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
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return;
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//Y must have exactly one connection, and it has to be a $mux cell.
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//We must have a direct bus connection from our Y to their A.
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const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
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pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
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if(y_loads.size() != 1)
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return;
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Cell* count_mux = *y_loads.begin();
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if(count_mux->type != "$mux")
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return;
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if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
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return;
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//B connection of the mux is our overflow value
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const RTLIL::SigSpec overflow = sigmap(count_mux->getPort("\\B"));
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if(!overflow.is_fully_const())
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return;
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int count_value = overflow.as_int();
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//S connection of the mux must come from an inverter (need not be the only load)
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const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S"));
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pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
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Cell* underflow_inv = NULL;
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for(auto c : muxsel_conns)
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{
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if(c->type != "$logic_not")
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continue;
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if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true))
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continue;
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underflow_inv = c;
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break;
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}
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if(underflow_inv == NULL)
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return;
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//Y connection of the mux must have exactly one load, the counter's internal register
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const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
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pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
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if(muxy_loads.size() != 1)
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return;
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Cell* count_reg = *muxy_loads.begin();
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if(count_reg->type != "$dff") //TODO: support dffr/dffs?
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return;
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if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
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return;
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//Register output must have exactly two loads, the inverter and ALU
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const RTLIL::SigSpec cnout = sigmap(count_reg->getPort("\\Q"));
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pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
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if(cnout_loads.size() != 2)
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return;
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if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true))
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return;
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if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true))
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return;
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//Register output net must have an INIT attribute equal to the count value
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auto rwire = cnout.as_wire();
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if(rwire->attributes.find("\\init") == rwire->attributes.end())
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return;
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int rinit = rwire->attributes["\\init"].as_int();
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if(rinit != count_value)
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return;
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//Figure out the final cell type based on the counter size
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string celltype = "\\GP_COUNT8";
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if(a_width > 8)
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celltype = "\\GP_COUNT14";
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//Log it
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total_counters ++;
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log(" Extracting %d-bit counter to %s hard macro\n", a_width, celltype.c_str());
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log(" Decrementer: %s\n", cell->name.c_str());
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log(" Output mux: %s\n", count_mux->name.c_str());
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log(" Register: %s\n", count_reg->name.c_str());
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log(" Comparator: %s\n", underflow_inv->name.c_str());
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log(" Count value: %d\n", count_value);
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/*
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log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell));
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if (GetSize(setctrl) == 1) {
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cell->setPort("\\ARST", setctrl);
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cell->setParam("\\ARST_POLARITY", setpol);
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} else {
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cell->setPort("\\ARST", clrctrl);
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cell->setParam("\\ARST_POLARITY", clrpol);
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}
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cell->type = "$adff";
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cell->unsetPort("\\SET");
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cell->unsetPort("\\CLR");
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cell->setParam("\\ARST_VALUE", reset_val);
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cell->unsetParam("\\SET_POLARITY");
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cell->unsetParam("\\CLR_POLARITY");
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return;
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*/
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}
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struct CountersPass : public Pass {
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@ -208,12 +257,17 @@ struct CountersPass : public Pass {
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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unsigned int total_counters = 0;
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for (auto module : design->selected_modules())
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{
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ModIndex index(module);
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for (auto cell : module->selected_cells())
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counters_worker(sigmap, module, cell);
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counters_worker(index, module, cell, total_counters);
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}
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if(total_counters)
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log("Extracted %u counters\n", total_counters);
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}
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} CountersPass;
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