mirror of https://github.com/YosysHQ/yosys.git
Simplify using module->ports, which is apparently sorted
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@ -2333,18 +2333,10 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
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dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true);
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dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true);
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f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
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f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
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int cnt = 0;
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int cnt = 0;
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int max_port_id = 0;
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for (auto port : module->ports) {
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for (auto wire : module->wires()) {
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Wire *wire = module->wire(port);
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max_port_id = std::max(wire->port_id, max_port_id);
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}
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std::vector<Wire *> wires(max_port_id + 1, nullptr);
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for (auto wire : module->wires()) {
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wires[wire->port_id] = wire;
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}
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for (int port_id = 1; port_id <= max_port_id; port_id++) {
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Wire *wire = wires[port_id];
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if (wire) {
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if (wire) {
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if (port_id != 1)
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if (port != module->ports[0])
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f << stringf(", ");
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f << stringf(", ");
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f << stringf("%s", id(wire->name).c_str());
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f << stringf("%s", id(wire->name).c_str());
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if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
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if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
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