From ace558e90c5a29179bf0d624057e433911ebb08a Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Sun, 17 Nov 2024 11:36:30 -0800 Subject: [PATCH] Simplify using module->ports, which is apparently sorted --- backends/verilog/verilog_backend.cc | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6602d96d7..a8dd356bc 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2333,18 +2333,10 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); int cnt = 0; - int max_port_id = 0; - for (auto wire : module->wires()) { - max_port_id = std::max(wire->port_id, max_port_id); - } - std::vector wires(max_port_id + 1, nullptr); - for (auto wire : module->wires()) { - wires[wire->port_id] = wire; - } - for (int port_id = 1; port_id <= max_port_id; port_id++) { - Wire *wire = wires[port_id]; + for (auto port : module->ports) { + Wire *wire = module->wire(port); if (wire) { - if (port_id != 1) + if (port != module->ports[0]) f << stringf(", "); f << stringf("%s", id(wire->name).c_str()); if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;