mirror of https://github.com/YosysHQ/yosys.git
Copy with 1'bx padding in $shiftx
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@ -178,7 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech
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// Only map if $shiftx exclusively covers the shift register
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if (shiftx->type == "$shiftx") {
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if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
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if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int())
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return false;
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// Due to padding the most significant bits of A may be 1'bx,
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// and if so, discount them
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if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) {
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const SigSpec A = shiftx->getPort("\\A");
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const int A_width = shiftx->getParam("\\A_WIDTH").as_int();
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for (int i = GetSize(taps); i < A_width; ++i)
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if (A[i] != RTLIL::Sx) return false;
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}
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else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
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return false;
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}
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else if (shiftx->type == "$mux") {
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