mirror of https://github.com/YosysHQ/yosys.git
Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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@ -51,12 +51,12 @@ USING_YOSYS_NAMESPACE
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#include "VeriLibrary.h"
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#include "VeriLibrary.h"
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#include "VeriExtensions.h"
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#include "VeriExtensions.h"
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#ifndef SYMBIOTIC_VERIFIC_API_VERSION
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#ifndef YOSYSHQ_VERIFIC_API_VERSION
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# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific."
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# error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
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#endif
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#endif
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#if SYMBIOTIC_VERIFIC_API_VERSION < 20201101
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#if YOSYSHQ_VERIFIC_API_VERSION < 20201201
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# error "Please update your version of Symbiotic EDA flavored Verific."
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# error "Please update your version of YosysHQ flavored Verific."
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#endif
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#endif
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#ifdef __clang__
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#ifdef __clang__
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@ -1471,7 +1471,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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continue;
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continue;
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}
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}
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if (inst->Type() == PRIM_SEDA_INITSTATE)
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if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
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{
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{
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SigBit initstate = module->Initstate(new_verific_id(inst));
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SigBit initstate = module->Initstate(new_verific_id(inst));
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SigBit sig_o = net_map_at(inst->GetOutput());
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SigBit sig_o = net_map_at(inst->GetOutput());
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@ -2199,7 +2199,7 @@ struct VerificPass : public Pass {
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log("\n");
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log("\n");
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log(" verific -app <application>..\n");
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log(" verific -app <application>..\n");
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log("\n");
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log("\n");
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log("Execute SEDA formal application on loaded Verilog files.\n");
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log("Execute YosysHQ formal application on loaded Verilog files.\n");
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log("\n");
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log("\n");
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log("Application options:\n");
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log("Application options:\n");
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log("\n");
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log("\n");
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@ -2250,11 +2250,11 @@ struct VerificPass : public Pass {
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log(" WARNING: Templates only available in commercial build.\n");
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log(" WARNING: Templates only available in commercial build.\n");
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log("\n");
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log("\n");
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#endif
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#endif
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log("Use Symbiotic EDA Suite if you need Yosys+Verifc.\n");
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log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n");
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log("https://www.symbioticeda.com/seda-suite\n");
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log("https://www.yosyshq.com/\n");
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log("\n");
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log("\n");
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log("Contact office@symbioticeda.com for free evaluation\n");
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log("Contact office@yosyshq.com for free evaluation\n");
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log("binaries of Symbiotic EDA Suite.\n");
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log("binaries of YosysHQ Tabby CAD Suite.\n");
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log("\n");
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log("\n");
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}
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}
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#ifdef YOSYS_ENABLE_VERIFIC
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#ifdef YOSYS_ENABLE_VERIFIC
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@ -2265,11 +2265,11 @@ struct VerificPass : public Pass {
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if (check_noverific_env())
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if (check_noverific_env())
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log_cmd_error("This version of Yosys is built without Verific support.\n"
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log_cmd_error("This version of Yosys is built without Verific support.\n"
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"\n"
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"\n"
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"Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
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"Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"
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"https://www.symbioticeda.com/seda-suite\n"
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"https://www.yosyshq.com/\n"
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"\n"
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"\n"
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"Contact office@symbioticeda.com for free evaluation\n"
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"Contact office@yosyshq.com for free evaluation\n"
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"binaries of Symbiotic EDA Suite.\n");
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"binaries of YosysHQ Tabby CAD Suite.\n");
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log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
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log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
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@ -2926,11 +2926,11 @@ struct VerificPass : public Pass {
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void execute(std::vector<std::string>, RTLIL::Design *) override {
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void execute(std::vector<std::string>, RTLIL::Design *) override {
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log_cmd_error("This version of Yosys is built without Verific support.\n"
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log_cmd_error("This version of Yosys is built without Verific support.\n"
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"\n"
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"\n"
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"Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
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"Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"
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"https://www.symbioticeda.com/seda-suite\n"
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"https://www.yosyshq.com/\n"
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"\n"
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"\n"
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"Contact office@symbioticeda.com for free evaluation\n"
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"Contact office@yosyshq.com for free evaluation\n"
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"binaries of Symbiotic EDA Suite.\n");
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"binaries of YosysHQ Tabby CAD Suite.\n");
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}
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}
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#endif
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#endif
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} VerificPass;
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} VerificPass;
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