mirror of https://github.com/YosysHQ/yosys.git
Merge df72f30141
into 29e8812bab
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commit
aca89c477e
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@ -78,7 +78,7 @@ struct SynthQuickLogicPass : public ScriptPass {
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}
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string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path;
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bool abc9, inferAdder, nobram, bramTypes, dsp;
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bool abc9, inferAdder, nobram, bramTypes, dsp, flatten;
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void clear_flags() override
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{
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@ -94,6 +94,7 @@ struct SynthQuickLogicPass : public ScriptPass {
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bramTypes = false;
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lib_path = "+/quicklogic/";
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dsp = true;
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flatten = true;
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}
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void set_scratchpad_defaults(RTLIL::Design *design) {
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@ -158,6 +159,10 @@ struct SynthQuickLogicPass : public ScriptPass {
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dsp = false;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -202,7 +207,8 @@ struct SynthQuickLogicPass : public ScriptPass {
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if (check_label("prepare")) {
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run("proc");
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run("flatten");
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if (flatten)
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run("flatten", "(unless -noflatten)");
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if (help_mode || family == "pp3") {
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run("tribuf -logic", " (for pp3)");
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}
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