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attributes.count() -> get_bool_attribute()

This commit is contained in:
Eddie Hung 2019-12-31 22:54:56 -08:00
parent 44d9fb0e7c
commit ac808c5e2a
2 changed files with 3 additions and 3 deletions
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2
backends/aiger/xaiger.cc
View File

@ -284,7 +284,7 @@ struct XAigerWriter
toposort.node(cell->name); toposort.node(cell->name);
if (inst_module->attributes.count("\\abc9_flop")) if (inst_module->get_bool_attribute("\\abc9_flop"))
flop_boxes.push_back(cell); flop_boxes.push_back(cell);
continue; continue;
} }

4
passes/techmap/abc9.cc
View File

@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
} }
RTLIL::Module* box_module = design->module(mapped_cell->type); RTLIL::Module* box_module = design->module(mapped_cell->type);
auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop"); auto abc9_flop = box_module && box_module->get_bool_attribute("\\abc9_flop");
for (auto &conn : mapped_cell->connections()) { for (auto &conn : mapped_cell->connections()) {
RTLIL::SigSpec newsig; RTLIL::SigSpec newsig;
for (auto c : conn.second.chunks()) { for (auto c : conn.second.chunks()) {
@ -988,7 +988,7 @@ struct Abc9Pass : public Pass {
for (auto cell : all_cells) { for (auto cell : all_cells) {
auto inst_module = design->module(cell->type); auto inst_module = design->module(cell->type);
if (!inst_module || !inst_module->attributes.count("\\abc9_flop") if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop")
|| cell->get_bool_attribute("\\abc9_keep")) || cell->get_bool_attribute("\\abc9_keep"))
continue; continue;