mirror of https://github.com/YosysHQ/yosys.git
Improved equiv_purge log output
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@ -80,7 +80,7 @@ struct EquivPurgeWorker
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Wire *wire = module->addWire(name, GetSize(sig));
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wire->port_input = true;
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module->connect(sig, wire);
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log(" Module input: %s\n", log_signal(wire));
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log(" Module input: %s (%s)\n", log_signal(wire), log_signal(sig));
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return module->addWire(NEW_ID, GetSize(sig));
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}
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}
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