mirror of https://github.com/YosysHQ/yosys.git
Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
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@ -29,3 +29,4 @@ $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cells.lib))
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$(eval $(call add_share_file,share,techlibs/common/cells.lib))
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$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
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$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
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$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
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@ -0,0 +1,10 @@
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module \$__ABC9_FF_ (input D, output Q);
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endmodule
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(* abc9_box *)
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module \$__ABC9_DELAY (input I, output O);
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parameter DELAY = 0;
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specify
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(I => O) = DELAY;
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endspecify
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endmodule
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