mirror of https://github.com/YosysHQ/yosys.git
smt2: emit smtlib2_comb_expr outputs after all inputs
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5f9a97d234
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@ -927,6 +927,7 @@ struct Smt2Worker
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}
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std::string smtlib2_inputs;
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std::vector<std::string> smtlib2_decls;
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if (is_smtlib2_module) {
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for (auto wire : module->wires()) {
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if (!wire->port_input)
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@ -968,11 +969,12 @@ struct Smt2Worker
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log_error("smtlib2_comb_expr is unsupported on multi-bit wires when -nobv is specified: wire %s.%s",
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log_id(module), log_id(wire));
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}
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auto &out_decls = is_smtlib2_comb_expr ? smtlib2_decls : decls;
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if (bvmode && GetSize(sig) > 1) {
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std::string sig_bv = is_smtlib2_comb_expr ? smtlib2_comb_expr : get_bv(sig);
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if (!comments.empty())
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decls.insert(decls.end(), comments.begin(), comments.end());
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decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
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out_decls.insert(out_decls.end(), comments.begin(), comments.end());
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out_decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
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get_id(module), get_id(wire), get_id(module), GetSize(sig), sig_bv.c_str()));
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if (wire->port_input)
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ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
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@ -983,16 +985,16 @@ struct Smt2Worker
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sig_bool.push_back(is_smtlib2_comb_expr ? smtlib2_comb_expr : get_bool(sig[i]));
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}
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if (!comments.empty())
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decls.insert(decls.end(), comments.begin(), comments.end());
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out_decls.insert(out_decls.end(), comments.begin(), comments.end());
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for (int i = 0; i < GetSize(sig); i++) {
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if (GetSize(sig) > 1) {
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decls.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n",
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out_decls.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n",
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get_id(module), get_id(wire), i, get_id(module), sig_bool[i].c_str()));
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if (wire->port_input)
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ex_input_eq.push_back(stringf(" (= (|%s_n %s %d| state) (|%s_n %s %d| other_state))",
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get_id(module), get_id(wire), i, get_id(module), get_id(wire), i));
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} else {
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decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n",
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out_decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n",
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get_id(module), get_id(wire), get_id(module), sig_bool[i].c_str()));
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if (wire->port_input)
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ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))",
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@ -1003,6 +1005,8 @@ struct Smt2Worker
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}
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}
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decls.insert(decls.end(), smtlib2_decls.begin(), smtlib2_decls.end());
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if (verbose) log("=> export logic associated with the initial state\n");
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vector<string> init_list;
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@ -5,6 +5,9 @@
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(declare-fun |smtlib2#0| (|smtlib2_s|) (_ BitVec 8)) ; \a
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; yosys-smt2-input a 8
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(define-fun |smtlib2_n a| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#0| state))
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(declare-fun |smtlib2#1| (|smtlib2_s|) (_ BitVec 8)) ; \b
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; yosys-smt2-input b 8
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(define-fun |smtlib2_n b| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#1| state))
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; yosys-smt2-output add 8
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(define-fun |smtlib2_n add| ((state |smtlib2_s|)) (_ BitVec 8) (let (
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(|a| (|smtlib2_n a| state))
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@ -12,9 +15,6 @@
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)
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(bvadd a b)
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))
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(declare-fun |smtlib2#1| (|smtlib2_s|) (_ BitVec 8)) ; \b
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; yosys-smt2-input b 8
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(define-fun |smtlib2_n b| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#1| state))
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; yosys-smt2-output eq 1
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(define-fun |smtlib2_n eq| ((state |smtlib2_s|)) Bool (let (
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(|a| (|smtlib2_n a| state))
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@ -1,5 +1,5 @@
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#!/bin/bash
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set -ex
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../../yosys -q -p 'read_verilog -formal smtlib2_module.v; prep; write_smt2 smtlib2_module.smt2'
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sed 's/; SMT-LIBv2 description generated by Yosys .*/; SMT-LIBv2 description generated by Yosys $VERSION/' smtlib2_module.smt2 > smtlib2_module-filtered.smt2
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sed 's/; SMT-LIBv2 description generated by Yosys .*/; SMT-LIBv2 description generated by Yosys $VERSION/;s/ *$//' smtlib2_module.smt2 > smtlib2_module-filtered.smt2
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diff -au smtlib2_module-expected.smt2 smtlib2_module-filtered.smt2
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