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clk2fflogic: Support all FF types.

This commit is contained in:
Marcelina Kościelnicka 2020-07-19 03:25:41 +02:00
parent 0c6d0d4b5d
commit abe4e9e607
20 changed files with 261 additions and 340 deletions
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290
passes/sat/clk2fflogic.cc
View File

@ -19,6 +19,8 @@
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/ffinit.h"
#include "kernel/ff.h"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
@ -80,19 +82,7 @@ struct Clk2fflogicPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
SigMap sigmap(module); SigMap sigmap(module);
dict<SigBit, State> initbits; FfInitVals initvals(&sigmap, module);
pool<SigBit> del_initbits;
for (auto wire : module->wires())
if (wire->attributes.count(ID::init) > 0)
{
Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
initbits[initsig[i]] = initval[i];
}
for (auto cell : vector<Cell*>(module->selected_cells())) for (auto cell : vector<Cell*>(module->selected_cells()))
{ {
@ -177,110 +167,83 @@ struct Clk2fflogicPass : public Pass {
cell->setPort(ID::WR_DATA, wr_data_port); cell->setPort(ID::WR_DATA, wr_data_port);
} }
if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) SigSpec qval;
{ if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
bool enpol = cell->parameters[ID::EN_POLARITY].as_bool(); FfData ff(&initvals, cell);
SigSpec sig_en = cell->getPort(ID::EN); if (ff.has_d && !ff.has_clk && !ff.has_en) {
SigSpec sig_d = cell->getPort(ID::D); // Already a $ff or $_FF_ cell.
SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
sig_en = wrap_async_control(module, sig_en, enpol);
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
module->addFf(NEW_ID, sig_q, past_q);
if (cell->type == ID($dlatch))
{
module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
}
else if (cell->type == ID($adlatch))
{
SigSpec t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
SigSpec arst = wrap_async_control(module, cell->getPort(ID::ARST), cell->parameters[ID::ARST_POLARITY].as_bool());
Const rstval = cell->parameters[ID::ARST_VALUE];
module->addMux(NEW_ID, t, rstval, arst, sig_q);
}
else
{
SigSpec t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
SigSpec s = wrap_async_control(module, cell->getPort(ID::SET), cell->parameters[ID::SET_POLARITY].as_bool());
t = module->Or(NEW_ID, t, s);
SigSpec c = wrap_async_control(module, cell->getPort(ID::CLR), cell->parameters[ID::CLR_POLARITY].as_bool());
c = module->Not(NEW_ID, c);
module->addAnd(NEW_ID, t, c, sig_q);
}
Const initval;
bool assign_initval = false;
for (int i = 0; i < GetSize(sig_d); i++) {
SigBit qbit = sigmap(sig_q[i]);
if (initbits.count(qbit)) {
initval.bits.push_back(initbits.at(qbit));
del_initbits.insert(qbit);
} else
initval.bits.push_back(State::Sx);
if (initval.bits.back() != State::Sx)
assign_initval = true;
}
if (assign_initval)
past_q->attributes[ID::init] = initval;
module->remove(cell);
continue; continue;
} }
bool word_dff = cell->type.in(ID($dff), ID($adff), ID($dffsr)); Wire *past_q = module->addWire(NEW_ID, ff.width);
if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_), if (!ff.is_fine) {
ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), module->addFf(NEW_ID, ff.sig_q, past_q);
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_), } else {
ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_), module->addFfGate(NEW_ID, ff.sig_q, past_q);
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_))) }
{ if (!ff.val_init.is_fully_undef())
bool clkpol; initvals.set_init(past_q, ff.val_init);
SigSpec clk;
if (word_dff) { if (ff.has_clk) {
clkpol = cell->parameters[ID::CLK_POLARITY].as_bool(); SigSpec sig_d = ff.sig_d;
clk = cell->getPort(ID::CLK); if (ff.has_srst && ff.has_en && ff.ce_over_srst) {
if (!ff.is_fine) {
if (ff.pol_srst)
sig_d = module->Mux(NEW_ID, sig_d, ff.val_srst, ff.sig_srst);
else
sig_d = module->Mux(NEW_ID, ff.val_srst, sig_d, ff.sig_srst);
} else {
if (ff.pol_srst)
sig_d = module->MuxGate(NEW_ID, sig_d, ff.val_srst[0], ff.sig_srst);
else
sig_d = module->MuxGate(NEW_ID, ff.val_srst[0], sig_d, ff.sig_srst);
}
}
if (ff.has_en) {
if (!ff.is_fine) {
if (ff.pol_en)
sig_d = module->Mux(NEW_ID, ff.sig_q, sig_d, ff.sig_en);
else
sig_d = module->Mux(NEW_ID, sig_d, ff.sig_q, ff.sig_en);
} else {
if (ff.pol_en)
sig_d = module->MuxGate(NEW_ID, ff.sig_q, sig_d, ff.sig_en);
else
sig_d = module->MuxGate(NEW_ID, sig_d, ff.sig_q, ff.sig_en);
}
}
if (ff.has_srst && !(ff.has_en && ff.ce_over_srst)) {
if (!ff.is_fine) {
if (ff.pol_srst)
sig_d = module->Mux(NEW_ID, sig_d, ff.val_srst, ff.sig_srst);
else
sig_d = module->Mux(NEW_ID, ff.val_srst, sig_d, ff.sig_srst);
} else {
if (ff.pol_srst)
sig_d = module->MuxGate(NEW_ID, sig_d, ff.val_srst[0], ff.sig_srst);
else
sig_d = module->MuxGate(NEW_ID, ff.val_srst[0], sig_d, ff.sig_srst);
} }
else {
if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_),
ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
clkpol = cell->type[6] == 'P';
else if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
clkpol = cell->type[8] == 'P';
else log_abort();
clk = cell->getPort(ID::C);
} }
Wire *past_clk = module->addWire(NEW_ID); Wire *past_clk = module->addWire(NEW_ID);
past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0; initvals.set_init(past_clk, ff.pol_clk ? State::S1 : State::S0);
if (word_dff) if (!ff.is_fine)
module->addFf(NEW_ID, clk, past_clk); module->addFf(NEW_ID, ff.sig_clk, past_clk);
else else
module->addFfGate(NEW_ID, clk, past_clk); module->addFfGate(NEW_ID, ff.sig_clk, past_clk);
SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n", log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
log_signal(clk), log_signal(sig_d), log_signal(sig_q)); log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
SigSpec clock_edge_pattern; SigSpec clock_edge_pattern;
if (clkpol) { if (ff.pol_clk) {
clock_edge_pattern.append(State::S0); clock_edge_pattern.append(State::S0);
clock_edge_pattern.append(State::S1); clock_edge_pattern.append(State::S1);
} else { } else {
@ -288,110 +251,69 @@ struct Clk2fflogicPass : public Pass {
clock_edge_pattern.append(State::S0); clock_edge_pattern.append(State::S0);
} }
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); SigSpec clock_edge = module->Eqx(NEW_ID, {ff.sig_clk, SigSpec(past_clk)}, clock_edge_pattern);
Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d)); Wire *past_d = module->addWire(NEW_ID, ff.width);
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q)); if (!ff.is_fine)
if (word_dff) {
module->addFf(NEW_ID, sig_d, past_d); module->addFf(NEW_ID, sig_d, past_d);
module->addFf(NEW_ID, sig_q, past_q); else
}
else {
module->addFfGate(NEW_ID, sig_d, past_d); module->addFfGate(NEW_ID, sig_d, past_d);
module->addFfGate(NEW_ID, sig_q, past_q);
}
if (cell->type == ID($adff)) if (!ff.val_init.is_fully_undef())
{ initvals.set_init(past_d, ff.val_init);
SigSpec arst = wrap_async_control(module, cell->getPort(ID::ARST), cell->parameters[ID::ARST_POLARITY].as_bool());
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
Const rstval = cell->parameters[ID::ARST_VALUE];
module->addMux(NEW_ID, qval, rstval, arst, sig_q); if (!ff.is_fine)
} qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
else else
if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_))) } else if (ff.has_d) {
{
SigSpec arst = wrap_async_control_gate(module, cell->getPort(ID::R), cell->type[7] == 'P');
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
SigBit rstval = (cell->type[8] == '1');
module->addMuxGate(NEW_ID, qval, rstval, arst, sig_q); log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
} log_id(module), log_id(cell), log_id(cell->type),
log_signal(ff.sig_en), log_signal(ff.sig_d), log_signal(ff.sig_q));
SigSpec sig_en = wrap_async_control(module, ff.sig_en, ff.pol_en);
if (!ff.is_fine)
qval = module->Mux(NEW_ID, past_q, ff.sig_d, sig_en);
else else
if (cell->type == ID($dffsr)) qval = module->MuxGate(NEW_ID, past_q, ff.sig_d, sig_en);
{ } else {
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
SigSpec setval = wrap_async_control(module, cell->getPort(ID::SET), cell->parameters[ID::SET_POLARITY].as_bool());
SigSpec clrval = wrap_async_control(module, cell->getPort(ID::CLR), cell->parameters[ID::CLR_POLARITY].as_bool());
log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
qval = past_q;
}
if (ff.has_sr) {
SigSpec setval = wrap_async_control(module, ff.sig_set, ff.pol_set);
SigSpec clrval = wrap_async_control(module, ff.sig_clr, ff.pol_clr);
if (!ff.is_fine) {
clrval = module->Not(NEW_ID, clrval); clrval = module->Not(NEW_ID, clrval);
qval = module->Or(NEW_ID, qval, setval); qval = module->Or(NEW_ID, qval, setval);
module->addAnd(NEW_ID, qval, clrval, sig_q); module->addAnd(NEW_ID, qval, clrval, ff.sig_q);
} } else {
else
if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
{
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
SigSpec setval = wrap_async_control_gate(module, cell->getPort(ID::S), cell->type[9] == 'P');
SigSpec clrval = wrap_async_control_gate(module, cell->getPort(ID::R), cell->type[10] == 'P');
clrval = module->NotGate(NEW_ID, clrval); clrval = module->NotGate(NEW_ID, clrval);
qval = module->OrGate(NEW_ID, qval, setval); qval = module->OrGate(NEW_ID, qval, setval);
module->addAndGate(NEW_ID, qval, clrval, sig_q); module->addAndGate(NEW_ID, qval, clrval, ff.sig_q);
}
else if (cell->type == ID($dff))
{
module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
} }
} else if (ff.has_arst) {
SigSpec arst = wrap_async_control(module, ff.sig_arst, ff.pol_arst);
if (!ff.is_fine)
module->addMux(NEW_ID, qval, ff.val_arst, arst, ff.sig_q);
else else
{ module->addMuxGate(NEW_ID, qval, ff.val_arst[0], arst, ff.sig_q);
module->addMuxGate(NEW_ID, past_q, past_d, clock_edge, sig_q); } else {
} module->connect(ff.sig_q, qval);
Const initval;
bool assign_initval = false;
for (int i = 0; i < GetSize(sig_d); i++) {
SigBit qbit = sigmap(sig_q[i]);
if (initbits.count(qbit)) {
initval.bits.push_back(initbits.at(qbit));
del_initbits.insert(qbit);
} else
initval.bits.push_back(State::Sx);
if (initval.bits.back() != State::Sx)
assign_initval = true;
}
if (assign_initval) {
past_d->attributes[ID::init] = initval;
past_q->attributes[ID::init] = initval;
} }
initvals.remove_init(ff.sig_q);
module->remove(cell); module->remove(cell);
continue; continue;
} }
} }
for (auto wire : module->wires())
if (wire->attributes.count(ID::init) > 0)
{
bool delete_initattr = true;
Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
if (del_initbits.count(initsig[i]) > 0)
initval[i] = State::Sx;
else if (initval[i] != State::Sx)
delete_initattr = false;
if (delete_initattr)
wire->attributes.erase(ID::init);
else
wire->attributes.at(ID::init) = initval;
}
} }
} }

1
tests/opt/opt_rmdff.ys
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@ -23,7 +23,6 @@ connect -port remove6 EN 1'b1
connect -port remove15 E 1'b1 connect -port remove15 E 1'b1
cd .. cd ..
dff2dffe -unmap
clk2fflogic clk2fflogic
opt_clean opt_clean

8
tests/techmap/dfflegalize_adff.ys
View File

@ -37,10 +37,10 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ADFFs. # Convert everything to ADFFs.

24
tests/techmap/dfflegalize_adff_init.ys
View File

@ -37,18 +37,18 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs. # Convert everything to ADFFs.

4
tests/techmap/dfflegalize_adlatch.ys
View File

@ -21,8 +21,8 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
# Convert everything to ADLATCHs. # Convert everything to ADLATCHs.

12
tests/techmap/dfflegalize_adlatch_init.ys
View File

@ -21,12 +21,12 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
# Convert everything to ADLATCHs. # Convert everything to ADLATCHs.

18
tests/techmap/dfflegalize_dff.ys
View File

@ -66,15 +66,15 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ x equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ x equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x
# Convert everything to DFFs. # Convert everything to DFFs.

56
tests/techmap/dfflegalize_dff_init.ys
View File

@ -66,34 +66,34 @@ EOT
design -save orig design -save orig
flatten flatten
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP1_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP1_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP1P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP1P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP1P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP1P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1
# Convert everything to DFFs. # Convert everything to DFFs.

8
tests/techmap/dfflegalize_dffsr.ys
View File

@ -24,10 +24,10 @@ EOT
design -save orig design -save orig
flatten flatten
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to ADFFs. # Convert everything to ADFFs.

24
tests/techmap/dfflegalize_dffsr_init.ys
View File

@ -41,18 +41,18 @@ EOT
design -save orig design -save orig
flatten flatten
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs. # Convert everything to ADFFs.

6
tests/techmap/dfflegalize_dlatch.ys
View File

@ -8,9 +8,9 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
# Convert everything to DFFs. # Convert everything to DFFs.

8
tests/techmap/dfflegalize_dlatch_const.ys
View File

@ -14,10 +14,10 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 01 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP?_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to ADFFs. # Convert everything to ADFFs.

16
tests/techmap/dfflegalize_dlatch_init.ys
View File

@ -8,14 +8,14 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
# Convert everything to DFFs. # Convert everything to DFFs.

4
tests/techmap/dfflegalize_dlatchsr.ys
View File

@ -10,8 +10,8 @@ endmodule
EOT EOT
design -save orig design -save orig
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
# Convert everything to ADLATCHs. # Convert everything to ADLATCHs.

12
tests/techmap/dfflegalize_dlatchsr_init.ys
View File

@ -23,12 +23,12 @@ EOT
design -save orig design -save orig
flatten flatten
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
# Convert everything to ADLATCHs. # Convert everything to ADLATCHs.

6
tests/techmap/dfflegalize_inv.ys
View File

@ -94,7 +94,7 @@ EOT
design -save orig design -save orig
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x
design -load postopt design -load postopt
select -assert-count 46 t:$_NOT_ select -assert-count 46 t:$_NOT_
@ -123,7 +123,7 @@ select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFS
design -load orig design -load orig
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x
design -load postopt design -load postopt
select -assert-count 122 t:$_NOT_ select -assert-count 122 t:$_NOT_
@ -166,7 +166,7 @@ endmodule
EOT EOT
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x
design -load postopt design -load postopt
select -assert-count 6 t:$_NOT_ select -assert-count 6 t:$_NOT_

2
tests/techmap/dfflegalize_mince.ys
View File

@ -22,7 +22,7 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3
design -load postopt design -load postopt
select -assert-count 4 t:$_DFFE_PP_ select -assert-count 4 t:$_DFFE_PP_

2
tests/techmap/dfflegalize_minsrst.ys
View File

@ -18,7 +18,7 @@ endmodule
EOT EOT
design -save orig design -save orig
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3 equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3
design -load postopt design -load postopt
select -assert-count 5 t:$_SDFF_PP0_ select -assert-count 5 t:$_SDFF_PP0_

12
tests/techmap/dfflegalize_sr.ys
View File

@ -9,12 +9,12 @@ endmodule
EOT EOT
design -save orig design -save orig
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ x equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to SRs. # Convert everything to SRs.

24
tests/techmap/dfflegalize_sr_init.ys
View File

@ -21,18 +21,18 @@ EOT
design -save orig design -save orig
flatten flatten
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 1
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1 #equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
# Convert everything to SRs. # Convert everything to SRs.