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Merge https://github.com/cliffordwolf/yosys

This commit is contained in:
Andrew Zonenberg 2016-04-22 19:07:55 -07:00
parent d90c1e9522 7311be4028
commit ab11f2aa70
118 changed files with 497 additions and 202 deletions
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14
backends/blif/blif.cc
View File

@ -317,6 +317,18 @@ struct BlifDumper
continue;
}
if (!config->icells_mode && cell->type == "$_DLATCH_N_") {
f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q")));
continue;
}
if (!config->icells_mode && cell->type == "$_DLATCH_P_") {
f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q")));
continue;
}
if (!config->icells_mode && cell->type == "$lut") {
f << stringf(".names");
auto &inputs = cell->getPort("\\A");
@ -448,7 +460,7 @@ struct BlifBackend : public Backend {
std::string false_type, false_out;
BlifDumperConfig config;
log_header("Executing BLIF backend.\n");
log_header(design, "Executing BLIF backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
backends/btor/btor.cc
View File

@ -1065,7 +1065,7 @@ struct BtorBackend : public Backend {
std::string false_type, false_out;
BtorDumperConfig config;
log_header("Executing BTOR backend.\n");
log_header(design, "Executing BTOR backend.\n");
size_t argidx=1;
extra_args(f, filename, args, argidx);

2
backends/edif/edif.cc
View File

@ -113,7 +113,7 @@ struct EdifBackend : public Backend {
}
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing EDIF backend.\n");
log_header(design, "Executing EDIF backend.\n");
std::string top_module_name;
std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;

2
backends/ilang/ilang_backend.cc
View File

@ -391,7 +391,7 @@ struct IlangBackend : public Backend {
{
bool selected = false;
log_header("Executing ILANG backend.\n");
log_header(design, "Executing ILANG backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

4
backends/intersynth/intersynth.cc
View File

@ -73,7 +73,7 @@ struct IntersynthBackend : public Backend {
}
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing INTERSYNTH backend.\n");
log_header(design, "Executing INTERSYNTH backend.\n");
log_push();
std::vector<std::string> libfiles;
@ -113,7 +113,7 @@ struct IntersynthBackend : public Backend {
}
if (libs.size() > 0)
log_header("Continuing INTERSYNTH backend.\n");
log_header(design, "Continuing INTERSYNTH backend.\n");
std::set<std::string> conntypes_code, celltypes_code;
std::string netlists_code;

2
backends/json/json.cc
View File

@ -463,7 +463,7 @@ struct JsonBackend : public Backend {
}
extra_args(f, filename, args, argidx);
log_header("Executing JSON backend.\n");
log_header(design, "Executing JSON backend.\n");
JsonWriter json_writer(*f, false, aig_mode);
json_writer.write_design(design);

2
backends/smt2/smt2.cc
View File

@ -758,7 +758,7 @@ struct Smt2Backend : public Backend {
std::ifstream template_f;
bool bvmode = false, memmode = false, regsmode = false, wiresmode = false, verbose = false;
log_header("Executing SMT2 backend.\n");
log_header(design, "Executing SMT2 backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
backends/smv/smv.cc
View File

@ -694,7 +694,7 @@ struct SmvBackend : public Backend {
std::ifstream template_f;
bool verbose = false;
log_header("Executing SMV backend.\n");
log_header(design, "Executing SMV backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
backends/spice/spice.cc
View File

@ -168,7 +168,7 @@ struct SpiceBackend : public Backend {
bool big_endian = false, use_inames = false;
std::string neg = "Vss", pos = "Vdd", ncpf = "_NC";
log_header("Executing SPICE backend.\n");
log_header(design, "Executing SPICE backend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
backends/verilog/verilog_backend.cc
View File

@ -1363,7 +1363,7 @@ struct VerilogBackend : public Backend {
}
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing Verilog backend.\n");
log_header(design, "Executing Verilog backend.\n");
norename = false;
noattr = false;

11
frontends/ast/ast.cc
View File

@ -146,6 +146,8 @@ std::string AST::type2str(AstNodeType type)
X(AST_ASSIGN_LE)
X(AST_CASE)
X(AST_COND)
X(AST_CONDX)
X(AST_CONDZ)
X(AST_DEFAULT)
X(AST_FOR)
X(AST_WHILE)
@ -501,6 +503,11 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
break;
case AST_CASE:
if (!children.empty() && children[0]->type == AST_CONDX)
fprintf(f, "%s" "casex (", indent.c_str());
else if (!children.empty() && children[0]->type == AST_CONDZ)
fprintf(f, "%s" "casez (", indent.c_str());
else
fprintf(f, "%s" "case (", indent.c_str());
children[0]->dumpVlog(f, "");
fprintf(f, ")\n");
@ -512,6 +519,8 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
break;
case AST_COND:
case AST_CONDX:
case AST_CONDZ:
for (auto child : children) {
if (child->type == AST_BLOCK) {
fprintf(f, ":\n");
@ -1033,7 +1042,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
if (stripped_name.substr(0, 9) == "$abstract")
stripped_name = stripped_name.substr(9);
log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
current_ast = NULL;
flag_dump_ast1 = false;

2
frontends/ast/ast.h
View File

@ -122,6 +122,8 @@ namespace AST
AST_ASSIGN_LE,
AST_CASE,
AST_COND,
AST_CONDX,
AST_CONDZ,
AST_DEFAULT,
AST_FOR,
AST_WHILE,

6
frontends/ast/genrtlil.cc
View File

@ -338,12 +338,14 @@ struct AST_INTERNAL::ProcessGenerator
case AST_CASE:
for (auto child : ast->children)
if (child != ast->children[0]) {
log_assert(child->type == AST_COND);
log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
collect_lvalues(reg, child, type_eq, type_le, false);
}
break;
case AST_COND:
case AST_CONDX:
case AST_CONDZ:
case AST_ALWAYS:
case AST_INITIAL:
for (auto child : ast->children)
@ -467,7 +469,7 @@ struct AST_INTERNAL::ProcessGenerator
{
if (child == ast->children[0])
continue;
log_assert(child->type == AST_COND);
log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
subst_lvalue_map.save();
subst_rvalue_map.save();

18
frontends/ast/simplify.cc
View File

@ -540,6 +540,18 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
}
if (type == AST_CONDX && children.size() > 0 && children.at(0)->type == AST_CONSTANT) {
for (auto &bit : children.at(0)->bits)
if (bit == State::Sz || bit == State::Sx)
bit = State::Sa;
}
if (type == AST_CONDZ && children.size() > 0 && children.at(0)->type == AST_CONSTANT) {
for (auto &bit : children.at(0)->bits)
if (bit == State::Sz)
bit = State::Sa;
}
if (const_fold && type == AST_CASE)
{
while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { }
@ -548,7 +560,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
new_children.push_back(children[0]);
for (int i = 1; i < GetSize(children); i++) {
AstNode *child = children[i];
log_assert(child->type == AST_COND);
log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
for (auto v : child->children) {
if (v->type == AST_DEFAULT)
goto keep_const_cond;
@ -1125,7 +1137,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *selected_case = NULL;
for (size_t i = 1; i < children.size(); i++)
{
log_assert(children.at(i)->type == AST_COND);
log_assert(children.at(i)->type == AST_COND || children.at(i)->type == AST_CONDX || children.at(i)->type == AST_CONDZ);
AstNode *this_genblock = NULL;
for (auto child : children.at(i)->children) {
@ -2984,7 +2996,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
for (size_t i = 1; i < stmt->children.size(); i++)
{
bool found_match = false;
log_assert(stmt->children.at(i)->type == AST_COND);
log_assert(stmt->children.at(i)->type == AST_COND || stmt->children.at(i)->type == AST_CONDX || stmt->children.at(i)->type == AST_CONDZ);
if (stmt->children.at(i)->children.front()->type == AST_DEFAULT) {
sel_case = stmt->children.at(i)->children.back();

6
frontends/blif/blifparse.cc
View File

@ -244,6 +244,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "fe"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else if (!strcmp(edge, "ah"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "al"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else {
no_latch_clock:
cell = module->addCell(NEW_ID, dff_name);
@ -399,7 +403,7 @@ struct BlifFrontend : public Frontend {
}
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing BLIF frontend.\n");
log_header(design, "Executing BLIF frontend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
frontends/ilang/ilang_frontend.cc
View File

@ -47,7 +47,7 @@ struct IlangFrontend : public Frontend {
}
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing ILANG frontend.\n");
log_header(design, "Executing ILANG frontend.\n");
extra_args(f, filename, args, 1);
log("Input filename: %s\n", filename.c_str());

2
frontends/liberty/liberty.cc
View File

@ -437,7 +437,7 @@ struct LibertyFrontend : public Frontend {
bool flag_ignore_miss_dir = false;
std::vector<std::string> attributes;
log_header("Executing Liberty frontend.\n");
log_header(design, "Executing Liberty frontend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
frontends/verific/verific.cc
View File

@ -850,7 +850,7 @@ struct VerificPass : public Pass {
#ifdef YOSYS_ENABLE_VERIFIC
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n");
log_header(design, "Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n");
Message::SetConsoleOutput(0);
Message::RegisterCallBackMsg(msg_func);

2
frontends/verilog/verilog_frontend.cc
View File

@ -186,7 +186,7 @@ struct VerilogFrontend : public Frontend {
formal_mode = false;
default_nettype_wire = true;
log_header("Executing Verilog-2005 frontend.\n");
log_header(design, "Executing Verilog-2005 frontend.\n");
args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());

8
frontends/verilog/verilog_parser.y
View File

@ -1094,7 +1094,9 @@ case_body:
case_item:
{
AstNode *node = new AstNode(AST_COND);
AstNode *node = new AstNode(
case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} case_select {
@ -1114,7 +1116,9 @@ gen_case_body:
gen_case_item:
{
AstNode *node = new AstNode(AST_COND);
AstNode *node = new AstNode(
case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} case_select {

4
frontends/vhdl2verilog/vhdl2verilog.cc
View File

@ -74,7 +74,7 @@ struct Vhdl2verilogPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing VHDL2VERILOG (importing VHDL designs using vhdl2verilog).\n");
log_header(design, "Executing VHDL2VERILOG (importing VHDL designs using vhdl2verilog).\n");
log_push();
std::string out_file, top_entity;
@ -173,7 +173,7 @@ struct Vhdl2verilogPass : public Pass {
Frontend::frontend_call(design, &ff, stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()), "verilog");
}
log_header("Removing temp directory `%s':\n", tempdir_name.c_str());
log_header(design, "Removing temp directory `%s':\n", tempdir_name.c_str());
remove_directory(tempdir_name);
log_pop();
}

18
kernel/driver.cc
View File

@ -213,6 +213,10 @@ int main(int argc, char **argv)
printf(" -A\n");
printf(" will call abort() at the end of the script. for debugging\n");
printf("\n");
printf(" -D <header_id>[:<filename>]\n");
printf(" dump the design when printing the specified log header to a file.\n");
printf(" yosys_dump_<header_id>.il is used as filename if none is specified.\n");
printf("\n");
printf(" -V\n");
printf(" print version information and exit\n");
printf("\n");
@ -233,7 +237,7 @@ int main(int argc, char **argv)
}
int opt;
while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:")) != -1)
while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:D:")) != -1)
{
switch (opt)
{
@ -315,6 +319,18 @@ int main(int argc, char **argv)
scriptfile = optarg;
scriptfile_tcl = true;
break;
case 'D':
{
auto args = split_tokens(optarg, ":");
if (GetSize(args) == 1)
args.push_back("yosys_dump_" + args[0] + ".il");
if (GetSize(args) != 2) {
fprintf(stderr, "Invalid number of tokens in -D.\n");
exit(1);
}
log_hdump[args[0]].insert(args[1]);
}
break;
default:
fprintf(stderr, "Run '%s -h' for help.\n", argv[0]);
exit(1);

20
kernel/log.cc
View File

@ -40,6 +40,7 @@ YOSYS_NAMESPACE_BEGIN
std::vector<FILE*> log_files;
std::vector<std::ostream*> log_streams;
std::map<std::string, std::set<std::string>> log_hdump;
FILE *log_errfile = NULL;
SHA1 *log_hasher = NULL;
@ -136,7 +137,7 @@ void logv(const char *format, va_list ap)
*f << str;
}
void logv_header(const char *format, va_list ap)
void logv_header(RTLIL::Design *design, const char *format, va_list ap)
{
bool pop_errfile = false;
@ -149,12 +150,21 @@ void logv_header(const char *format, va_list ap)
pop_errfile = true;
}
std::string header_id;
for (int c : header_count)
log("%d.", c);
log(" ");
header_id += stringf("%s%d", header_id.empty() ? "" : ".", c);
log("%s. ", header_id.c_str());
logv(format, ap);
log_flush();
if (log_hdump.count(header_id) && design != nullptr)
for (auto &filename : log_hdump.at(header_id)) {
log("Dumping current design to '%s'.\n", filename.c_str());
Pass::call(design, {"dump", "-o", filename});
}
if (pop_errfile)
log_files.pop_back();
}
@ -206,11 +216,11 @@ void log(const char *format, ...)
va_end(ap);
}
void log_header(const char *format, ...)
void log_header(RTLIL::Design *design, const char *format, ...)
{
va_list ap;
va_start(ap, format);
logv_header(format, ap);
logv_header(design, format, ap);
va_end(ap);
}

5
kernel/log.h
View File

@ -47,6 +47,7 @@ struct log_cmd_error_exception { };
extern std::vector<FILE*> log_files;
extern std::vector<std::ostream*> log_streams;
extern std::map<std::string, std::set<std::string>> log_hdump;
extern FILE *log_errfile;
extern SHA1 *log_hasher;
@ -58,12 +59,12 @@ extern int log_verbose_level;
extern string log_last_error;
void logv(const char *format, va_list ap);
void logv_header(const char *format, va_list ap);
void logv_header(RTLIL::Design *design, const char *format, va_list ap);
void logv_warning(const char *format, va_list ap);
YS_NORETURN void logv_error(const char *format, va_list ap) YS_ATTRIBUTE(noreturn);
void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
void log_header(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));
void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);

2
kernel/register.cc
View File

@ -165,7 +165,7 @@ void Pass::call(RTLIL::Design *design, std::string command)
while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' ||
cmd_buf.back() == '\r' || cmd_buf.back() == '\n'))
cmd_buf.resize(cmd_buf.size()-1);
log_header("Shell command: %s\n", cmd_buf.c_str());
log_header(design, "Shell command: %s\n", cmd_buf.c_str());
int retCode = run_command(cmd_buf);
if (retCode != 0)
log_cmd_error("Shell command returned error code %d.\n", retCode);

2
manual/CHAPTER_Prog/stubnets.cc
View File

@ -103,7 +103,7 @@ struct StubnetsPass : public Pass {
// variables to mirror information from passed options
bool report_bits = 0;
log_header("Executing STUBNETS pass (find stub nets).\n");
log_header(design, "Executing STUBNETS pass (find stub nets).\n");
// parse options
size_t argidx;

2
manual/PRESENTATION_Prog.tex
View File

@ -477,7 +477,7 @@ log("Name of this module: %s\n", log_id(module->name));
\medskip
Use {\tt log\_header()} and {\tt log\_push()}/{\tt log\_pop()} to structure log messages:
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
log_header("Doing important stuff!\n");
log_header(design, "Doing important stuff!\n");
log_push();
for (int i = 0; i < 10; i++)
log("Log message #%d.\n", i);

2
manual/PRESENTATION_Prog/my_cmd.cc
View File

@ -65,7 +65,7 @@ struct Test2Pass : public Pass {
log("Mapped signal x: %s\n", log_signal(sigmap(x)));
log_header("Doing important stuff!\n");
log_header(design, "Doing important stuff!\n");
log_push();
for (int i = 0; i < 10; i++)
log("Log message #%d.\n", i);

2
passes/cmds/check.cc
View File

@ -68,7 +68,7 @@ struct CheckPass : public Pass {
}
extra_args(args, argidx, design);
log_header("Executing CHECK pass (checking for obvious problems).\n");
log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
for (auto module : design->selected_whole_modules_warn())
{

2
passes/cmds/connwrappers.cc
View File

@ -198,7 +198,7 @@ struct ConnwrappersPass : public Pass {
}
extra_args(args, argidx, design);
log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
log_header(design, "Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))

2
passes/cmds/cover.cc
View File

@ -124,7 +124,7 @@ struct CoverPass : public Pass {
extra_args(args, argidx, design);
if (do_log) {
log_header("Printing code coverage counters.\n");
log_header(design, "Printing code coverage counters.\n");
log("\n");
}

2
passes/cmds/qwp.cc
View File

@ -787,7 +787,7 @@ struct QwpPass : public Pass {
QwpConfig config;
xorshift32_state = 123456789;
log_header("Executing QWP pass (quadratic wirelength placer).\n");
log_header(design, "Executing QWP pass (quadratic wirelength placer).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/cmds/scc.cc
View File

@ -264,7 +264,7 @@ struct SccPass : public Pass {
int maxDepth = -1;
int expect = -1;
log_header("Executing SCC pass (detecting logic loops).\n");
log_header(design, "Executing SCC pass (detecting logic loops).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

4
passes/cmds/show.cc
View File

@ -651,7 +651,7 @@ struct ShowPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Generating Graphviz representation of design.\n");
log_header(design, "Generating Graphviz representation of design.\n");
log_push();
std::vector<std::pair<std::string, RTLIL::Selection>> color_selections;
@ -784,7 +784,7 @@ struct ShowPass : public Pass {
}
if (libs.size() > 0)
log_header("Continuing show pass.\n");
log_header(design, "Continuing show pass.\n");
std::string dot_file = stringf("%s.dot", prefix.c_str());
std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());

2
passes/cmds/splice.cc
View File

@ -341,7 +341,7 @@ struct SplicePass : public Pass {
if (!ports.empty() && !no_ports.empty())
log_cmd_error("The options -port and -no_port are exclusive!\n");
log_header("Executing SPLICE pass (creating cells for signal splicing).\n");
log_header(design, "Executing SPLICE pass (creating cells for signal splicing).\n");
for (auto &mod_it : design->modules_)
{

2
passes/cmds/splitnets.cc
View File

@ -109,7 +109,7 @@ struct SplitnetsPass : public Pass {
bool flag_driver = false;
std::string format = "[]:";
log_header("Executing SPLITNETS pass (splitting up multi-bit signals).\n");
log_header(design, "Executing SPLITNETS pass (splitting up multi-bit signals).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
passes/cmds/stat.cc
View File

@ -232,7 +232,7 @@ struct StatPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Printing statistics.\n");
log_header(design, "Printing statistics.\n");
bool width_mode = false;
RTLIL::Module *top_mod = NULL;

2
passes/cmds/torder.cc
View File

@ -48,7 +48,7 @@ struct TorderPass : public Pass {
bool noautostop = false;
dict<IdString, pool<IdString>> stop_db;
log_header("Executing TORDER pass (print cells in topological order).\n");
log_header(design, "Executing TORDER pass (print cells in topological order).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/equiv/equiv_induct.cc
View File

@ -198,7 +198,7 @@ struct EquivInductPass : public Pass {
bool model_undef = false;
int max_seq = 4;
log_header("Executing EQUIV_INDUCT pass.\n");
log_header(design, "Executing EQUIV_INDUCT pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/equiv/equiv_make.cc
View File

@ -464,7 +464,7 @@ struct EquivMakePass : public Pass {
worker.read_blacklists();
worker.read_encfiles();
log_header("Executing EQUIV_MAKE pass (creating equiv checking module).\n");
log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n");
worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2]));
worker.run();

2
passes/equiv/equiv_mark.cc
View File

@ -218,7 +218,7 @@ struct EquivMarkPass : public Pass {
}
virtual void execute(std::vector<std::string> args, Design *design)
{
log_header("Executing EQUIV_MARK pass.\n");
log_header(design, "Executing EQUIV_MARK pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/equiv/equiv_miter.cc
View File

@ -333,7 +333,7 @@ struct EquivMiterPass : public Pass {
found_two_modules:
log_cmd_error("Exactly one module must be selected for 'equiv_miter'!\n");
log_header("Executing EQUIV_MITER pass.\n");
log_header(design, "Executing EQUIV_MITER pass.\n");
worker.miter_module = design->addModule(worker.miter_name);
worker.run();

2
passes/equiv/equiv_purge.cc
View File

@ -189,7 +189,7 @@ struct EquivPurgePass : public Pass {
}
virtual void execute(std::vector<std::string> args, Design *design)
{
log_header("Executing EQUIV_PURGE pass.\n");
log_header(design, "Executing EQUIV_PURGE pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/equiv/equiv_remove.cc
View File

@ -46,7 +46,7 @@ struct EquivRemovePass : public Pass {
bool mode_gate = false;
int remove_count = 0;
log_header("Executing EQUIV_REMOVE pass.\n");
log_header(design, "Executing EQUIV_REMOVE pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/equiv/equiv_simple.cc
View File

@ -277,7 +277,7 @@ struct EquivSimplePass : public Pass {
int success_counter = 0;
int max_seq = 1;
log_header("Executing EQUIV_SIMPLE pass.\n");
log_header(design, "Executing EQUIV_SIMPLE pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/equiv/equiv_status.cc
View File

@ -41,7 +41,7 @@ struct EquivStatusPass : public Pass {
bool assert_mode = false;
int unproven_count = 0;
log_header("Executing EQUIV_STATUS pass.\n");
log_header(design, "Executing EQUIV_STATUS pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/equiv/equiv_struct.cc
View File

@ -321,7 +321,7 @@ struct EquivStructPass : public Pass {
bool mode_fwd = false;
int max_iter = -1;
log_header("Executing EQUIV_STRUCT pass.\n");
log_header(design, "Executing EQUIV_STRUCT pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/fsm/fsm.cc
View File

@ -76,7 +76,7 @@ struct FsmPass : public Pass {
std::string encfile_opt;
std::string encoding_opt;
log_header("Executing FSM pass (extract and optimize FSM).\n");
log_header(design, "Executing FSM pass (extract and optimize FSM).\n");
log_push();
size_t argidx;

2
passes/fsm/fsm_detect.cc
View File

@ -154,7 +154,7 @@ struct FsmDetectPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing FSM_DETECT pass (finding FSMs in design).\n");
log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
extra_args(args, 1, design);
CellTypes ct;

2
passes/fsm/fsm_expand.cc
View File

@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
log_header(design, "Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_) {

2
passes/fsm/fsm_export.cc
View File

@ -152,7 +152,7 @@ struct FsmExportPass : public Pass {
bool flag_origenc = false;
size_t argidx;
log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
log_header(design, "Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
for (argidx = 1; argidx < args.size(); argidx++) {
arg = args[argidx];

2
passes/fsm/fsm_extract.cc
View File

@ -416,7 +416,7 @@ struct FsmExtractPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing FSM_EXTRACT pass (extracting FSM from design).\n");
log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
extra_args(args, 1, design);
CellTypes ct;

2
passes/fsm/fsm_info.cc
View File

@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)

2
passes/fsm/fsm_map.cc
View File

@ -335,7 +335,7 @@ struct FsmMapPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_) {

2
passes/fsm/fsm_opt.cc
View File

@ -336,7 +336,7 @@ struct FsmOptPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n");
log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_) {

2
passes/fsm/fsm_recode.cc
View File

@ -157,7 +157,7 @@ struct FsmRecodePass : public Pass {
FILE *encfile = NULL;
std::string default_encoding;
log_header("Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");
log_header(design, "Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];

8
passes/hierarchy/hierarchy.cc
View File

@ -396,7 +396,7 @@ struct HierarchyPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing HIERARCHY pass (managing design hierarchy).\n");
log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");
bool flag_check = false;
bool purge_lib = false;
@ -506,7 +506,7 @@ struct HierarchyPass : public Pass {
top_mod = mod_it.second;
if (top_mod == nullptr && auto_top_mode) {
log_header("Finding top of design hierarchy..\n");
log_header(design, "Finding top of design hierarchy..\n");
dict<Module*, int> db;
for (Module *mod : design->selected_modules()) {
int score = find_top_mod_score(design, mod, db);
@ -525,7 +525,7 @@ struct HierarchyPass : public Pass {
std::set<RTLIL::Module*> used_modules;
if (top_mod != NULL) {
log_header("Analyzing design hierarchy..\n");
log_header(design, "Analyzing design hierarchy..\n");
hierarchy_worker(design, used_modules, top_mod, 0);
} else {
for (auto mod : design->modules())
@ -539,7 +539,7 @@ struct HierarchyPass : public Pass {
}
if (top_mod != NULL) {
log_header("Analyzing design hierarchy..\n");
log_header(design, "Analyzing design hierarchy..\n");
hierarchy_clean(design, top_mod, purge_lib);
}

2
passes/hierarchy/singleton.cc
View File

@ -43,7 +43,7 @@ struct SingletonPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing SINGLETON pass (creating singleton modules).\n");
log_header(design, "Executing SINGLETON pass (creating singleton modules).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

6
passes/hierarchy/submod.cc
View File

@ -298,7 +298,7 @@ struct SubmodPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push();
std::string opt_name;
@ -321,7 +321,7 @@ struct SubmodPass : public Pass {
if (opt_name.empty())
{
Pass::call(design, "opt_clean");
log_header("Continuing SUBMOD pass.\n");
log_header(design, "Continuing SUBMOD pass.\n");
std::set<RTLIL::IdString> handled_modules;
@ -356,7 +356,7 @@ struct SubmodPass : public Pass {
log("Nothing selected -> do nothing.\n");
else {
Pass::call_on_module(design, module, "opt_clean");
log_header("Continuing SUBMOD pass.\n");
log_header(design, "Continuing SUBMOD pass.\n");
SubmodWorker worker(design, module, copy_mode, opt_name);
}
}

2
passes/memory/memory.cc
View File

@ -53,7 +53,7 @@ struct MemoryPass : public Pass {
bool flag_nordff = false;
string memory_bram_opts;
log_header("Executing MEMORY pass.\n");
log_header(design, "Executing MEMORY pass.\n");
log_push();
size_t argidx;

2
passes/memory/memory_bram.cc
View File

@ -1211,7 +1211,7 @@ struct MemoryBramPass : public Pass {
{
rules_t rules;
log_header("Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
log_header(design, "Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/memory/memory_collect.cc
View File

@ -247,7 +247,7 @@ struct MemoryCollectPass : public Pass {
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))

2
passes/memory/memory_dff.cc
View File

@ -283,7 +283,7 @@ struct MemoryDffPass : public Pass {
{
bool flag_wr_only = false;
log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/memory/memory_map.cc
View File

@ -363,7 +363,7 @@ struct MemoryMapPass : public Pass {
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
extra_args(args, 1, design);
for (auto mod : design->selected_modules())
MemoryMapWorker(design, mod);

43
passes/memory/memory_share.cc
View File

@ -43,7 +43,7 @@ struct MemoryShareWorker
CellTypes cone_ct;
std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux;
std::map<std::set<std::map<RTLIL::SigBit, bool>>, RTLIL::SigBit> conditions_logic_cache;
std::map<pair<std::set<std::map<SigBit, bool>>, SigBit>, SigBit> conditions_logic_cache;
// -----------------------------------------------------------------
@ -109,10 +109,12 @@ struct MemoryShareWorker
return false;
}
RTLIL::SigBit conditions_to_logic(std::set<std::map<RTLIL::SigBit, bool>> &conditions, int &created_conditions)
RTLIL::SigBit conditions_to_logic(std::set<std::map<RTLIL::SigBit, bool>> &conditions, SigBit olden, int &created_conditions)
{
if (conditions_logic_cache.count(conditions))
return conditions_logic_cache.at(conditions);
auto key = make_pair(conditions, olden);
if (conditions_logic_cache.count(key))
return conditions_logic_cache.at(key);
RTLIL::SigSpec terms;
for (auto &cond : conditions) {
@ -125,13 +127,16 @@ struct MemoryShareWorker
created_conditions++;
}
if (terms.size() == 0)
if (olden.wire != nullptr || olden != State::S1)
terms.append(olden);
if (GetSize(terms) == 0)
terms = State::S1;
if (terms.size() > 1)
if (GetSize(terms) > 1)
terms = module->ReduceAnd(NEW_ID, terms);
return conditions_logic_cache[conditions] = terms;
return conditions_logic_cache[key] = terms;
}
void translate_rd_feedback_to_en(std::string memid, std::vector<RTLIL::Cell*> &rd_ports, std::vector<RTLIL::Cell*> &wr_ports)
@ -140,15 +145,14 @@ struct MemoryShareWorker
std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map;
std::set<RTLIL::SigBit> non_feedback_nets;
for (auto wire_it : module->wires_)
if (wire_it.second->port_output) {
std::vector<RTLIL::SigBit> bits = RTLIL::SigSpec(wire_it.second);
for (auto wire : module->wires())
if (wire->port_output) {
std::vector<RTLIL::SigBit> bits = sigmap(wire);
non_feedback_nets.insert(bits.begin(), bits.end());
}
for (auto cell_it : module->cells_)
for (auto cell : module->cells())
{
RTLIL::Cell *cell = cell_it.second;
bool ignore_data_port = false;
if (cell->type == "$mux" || cell->type == "$pmux")
@ -173,7 +177,7 @@ struct MemoryShareWorker
cell->parameters.at("\\MEMID").decode_string() == memid)
ignore_data_port = true;
for (auto conn : cell_it.second->connections())
for (auto conn : cell->connections())
{
if (ignore_data_port && conn.first == "\\DATA")
continue;
@ -240,13 +244,8 @@ struct MemoryShareWorker
std::map<RTLIL::SigBit, bool> state;
std::set<std::map<RTLIL::SigBit, bool>> conditions;
if (cell_en[i].wire != NULL) {
state[cell_en[i]] = false;
conditions.insert(state);
}
find_data_feedback(async_rd_bits.at(sig_addr).at(i), cell_data[i], state, conditions);
cell_en[i] = conditions_to_logic(conditions, created_conditions);
cell_en[i] = conditions_to_logic(conditions, cell_en[i], created_conditions);
}
if (created_conditions) {
@ -666,10 +665,8 @@ struct MemoryShareWorker
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
sigmap_xmux = sigmap;
for (auto &it : module->cells_)
for (auto cell : module->cells())
{
RTLIL::Cell *cell = it.second;
if (cell->type == "$memrd")
memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell);
@ -750,7 +747,7 @@ struct MemorySharePass : public Pass {
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
extra_args(args, 1, design);
for (auto module : design->selected_modules())
MemoryShareWorker(design, module);

2
passes/memory/memory_unpack.cc
View File

@ -138,7 +138,7 @@ struct MemoryUnpackPass : public Pass {
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))

8
passes/opt/opt.cc
View File

@ -71,7 +71,7 @@ struct OptPass : public Pass {
std::string opt_merge_args;
bool fast_mode = false;
log_header("Executing OPT pass (performing simple optimizations).\n");
log_header(design, "Executing OPT pass (performing simple optimizations).\n");
log_push();
size_t argidx;
@ -132,7 +132,7 @@ struct OptPass : public Pass {
if (design->scratchpad_get_bool("opt.did_something") == false)
break;
Pass::call(design, "opt_clean" + opt_clean_args);
log_header("Rerunning OPT passes. (Removed registers in this run.)\n");
log_header(design, "Rerunning OPT passes. (Removed registers in this run.)\n");
}
Pass::call(design, "opt_clean" + opt_clean_args);
}
@ -150,7 +150,7 @@ struct OptPass : public Pass {
Pass::call(design, "opt_expr" + opt_expr_args);
if (design->scratchpad_get_bool("opt.did_something") == false)
break;
log_header("Rerunning OPT passes. (Maybe there is more to do..)\n");
log_header(design, "Rerunning OPT passes. (Maybe there is more to do..)\n");
}
}
@ -158,7 +158,7 @@ struct OptPass : public Pass {
design->sort();
design->check();
log_header(fast_mode ? "Finished fast OPT passes.\n" : "Finished OPT passes. (There is nothing left to do.)\n");
log_header(design, fast_mode ? "Finished fast OPT passes.\n" : "Finished OPT passes. (There is nothing left to do.)\n");
log_pop();
}
} OptPass;

2
passes/opt/opt_clean.cc
View File

@ -380,7 +380,7 @@ struct OptCleanPass : public Pass {
{
bool purge_mode = false;
log_header("Executing OPT_CLEAN pass (remove unused cells and wires).\n");
log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
log_push();
size_t argidx;

76
passes/opt/opt_expr.cc
View File

@ -342,6 +342,68 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", "\\R", assign_map, invert_map);
}
bool detect_const_and = false;
bool detect_const_or = false;
if (cell->type.in("$reduce_and", "$_AND_"))
detect_const_and = true;
if (cell->type.in("$and", "$logic_and") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1)
detect_const_and = true;
if (cell->type.in("$reduce_or", "$reduce_bool", "$_OR_"))
detect_const_or = true;
if (cell->type.in("$or", "$logic_or") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1)
detect_const_or = true;
if (detect_const_and || detect_const_or)
{
pool<SigBit> input_bits = assign_map(cell->getPort("\\A")).to_sigbit_pool();
bool found_zero = false, found_one = false, found_inv = false;
if (cell->hasPort("\\B")) {
vector<SigBit> more_bits = assign_map(cell->getPort("\\B")).to_sigbit_vector();
input_bits.insert(more_bits.begin(), more_bits.end());
}
for (auto bit : input_bits) {
if (bit == State::S0)
found_zero = true;
if (bit == State::S1)
found_one = true;
if (invert_map.count(bit) && input_bits.count(invert_map.at(bit)))
found_inv = true;
}
if (detect_const_and && (found_zero || found_inv)) {
cover("opt.opt_expr.const_and");
replace_cell(assign_map, module, cell, "const_and", "\\Y", RTLIL::State::S0);
goto next_cell;
}
if (detect_const_or && (found_one || found_inv)) {
cover("opt.opt_expr.const_or");
replace_cell(assign_map, module, cell, "const_or", "\\Y", RTLIL::State::S1);
goto next_cell;
}
}
if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor", "$neg") &&
GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\Y")) == 1)
{
if (cell->type == "$reduce_xnor") {
cover("opt.opt_expr.reduce_xnor_not");
log("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type = "$not";
} else {
cover("opt.opt_expr.unary_buffer");
replace_cell(assign_map, module, cell, "unary_buffer", "\\Y", cell->getPort("\\A"));
}
goto next_cell;
}
if (do_fine)
{
if (cell->type == "$not" || cell->type == "$pos" ||
@ -428,18 +490,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
}
if (cell->type == "$logic_or" && (assign_map(cell->getPort("\\A")) == RTLIL::State::S1 || assign_map(cell->getPort("\\B")) == RTLIL::State::S1)) {
cover("opt.opt_expr.one_high");
replace_cell(assign_map, module, cell, "one high", "\\Y", RTLIL::State::S1);
goto next_cell;
}
if (cell->type == "$logic_and" && (assign_map(cell->getPort("\\A")) == RTLIL::State::S0 || assign_map(cell->getPort("\\B")) == RTLIL::State::S0)) {
cover("opt.opt_expr.one_low");
replace_cell(assign_map, module, cell, "one low", "\\Y", RTLIL::State::S0);
goto next_cell;
}
if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" ||
cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" ||
cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt" ||
@ -1101,7 +1151,7 @@ struct OptExprPass : public Pass {
bool do_fine = false;
bool keepdc = false;
log_header("Executing OPT_EXPR pass (perform const folding).\n");
log_header(design, "Executing OPT_EXPR pass (perform const folding).\n");
log_push();
size_t argidx;

2
passes/opt/opt_merge.cc
View File

@ -348,7 +348,7 @@ struct OptMergePass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT_MERGE pass (detect identical cells).\n");
log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n");
bool mode_nomux = false;
bool mode_share_all = false;

2
passes/opt/opt_muxtree.cc
View File

@ -464,7 +464,7 @@ struct OptMuxtreePass : public Pass {
}
virtual void execute(vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
extra_args(args, 1, design);
int total_count = 0;

2
passes/opt/opt_reduce.cc
View File

@ -354,7 +354,7 @@ struct OptReducePass : public Pass {
{
bool do_fine = false;
log_header("Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");
log_header(design, "Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/opt/opt_rmdff.cc
View File

@ -191,7 +191,7 @@ struct OptRmdffPass : public Pass {
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
int total_count = 0;
log_header("Executing OPT_RMDFF pass (remove dff with constant values).\n");
log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
extra_args(args, 1, design);

55
passes/opt/share.cc
View File

@ -793,10 +793,59 @@ struct ShareWorker
return true;
}
void optimize_activation_patterns(pool<ssc_pair_t> & /* patterns */)
void optimize_activation_patterns(pool<ssc_pair_t> &patterns)
{
// TODO: Remove patterns that are contained in other patterns
// TODO: Consolidate pairs of patterns that only differ in the value for one signal bit
dict<SigSpec, pool<Const>> db;
bool did_something = false;
for (auto const &p : patterns)
{
auto &sig = p.first;
auto &val = p.second;
int len = GetSize(sig);
for (int i = 0; i < len; i++)
{
auto otherval = val;
if (otherval.bits[i] == State::S0)
otherval.bits[i] = State::S1;
else if (otherval.bits[i] == State::S1)
otherval.bits[i] = State::S0;
else
continue;
if (db[sig].count(otherval))
{
auto newsig = sig;
newsig.remove(i);
auto newval = val;
newval.bits.erase(newval.bits.begin() + i);
db[newsig].insert(newval);
db[sig].erase(otherval);
did_something = true;
goto next_pattern;
}
}
db[sig].insert(val);
next_pattern:;
}
if (!did_something)
return;
patterns.clear();
for (auto &it : db)
for (auto &val : it.second)
patterns.insert(make_pair(it.first, val));
optimize_activation_patterns(patterns);
}
const pool<ssc_pair_t> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent)
@ -1451,7 +1500,7 @@ struct SharePass : public Pass {
config.generic_other_ops.insert("$alu");
config.generic_other_ops.insert("$macc");
log_header("Executing SHARE pass (SAT-based resource sharing).\n");
log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/opt/wreduce.cc
View File

@ -371,7 +371,7 @@ struct WreducePass : public Pass {
{
WreduceConfig config;
log_header("Executing WREDUCE pass (reducing word size of cells).\n");
log_header(design, "Executing WREDUCE pass (reducing word size of cells).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/proc/proc.cc
View File

@ -57,7 +57,7 @@ struct ProcPass : public Pass {
{
std::string global_arst;
log_header("Executing PROC pass (convert processes to netlists).\n");
log_header(design, "Executing PROC pass (convert processes to netlists).\n");
log_push();
size_t argidx;

2
passes/proc/proc_arst.cc
View File

@ -226,7 +226,7 @@ struct ProcArstPass : public Pass {
std::string global_arst;
bool global_arst_neg = false;
log_header("Executing PROC_ARST pass (detect async resets in processes).\n");
log_header(design, "Executing PROC_ARST pass (detect async resets in processes).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
passes/proc/proc_clean.cc
View File

@ -156,7 +156,7 @@ struct ProcCleanPass : public Pass {
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
int total_count = 0;
log_header("Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
log_header(design, "Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
extra_args(args, 1, design);

2
passes/proc/proc_dff.cc
View File

@ -369,7 +369,7 @@ struct ProcDffPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing PROC_DFF pass (convert process syncs to FFs).\n");
log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n");
extra_args(args, 1, design);

2
passes/proc/proc_dlatch.cc
View File

@ -292,7 +292,7 @@ struct ProcDlatchPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing PROC_DLATCH pass (convert process syncs to latches).\n");
log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n");
extra_args(args, 1, design);

31
passes/proc/proc_init.cc
View File

@ -61,13 +61,28 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
int offset = 0;
for (auto &lhs_c : lhs.chunks()) {
if (lhs_c.wire != NULL) {
RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
if (value.size() != lhs_c.wire->width)
log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
lhs_c.wire->attributes["\\init"] = value.as_const();
for (auto &lhs_c : lhs.chunks())
{
if (lhs_c.wire != nullptr)
{
SigSpec valuesig = rhs.extract(offset, lhs_c.width);
if (!valuesig.is_fully_const())
log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
Const value = valuesig.as_const();
Const &wireinit = lhs_c.wire->attributes["\\init"];
while (GetSize(wireinit.bits) < lhs_c.wire->width)
wireinit.bits.push_back(State::Sx);
for (int i = 0; i < lhs_c.width; i++) {
auto &initbit = wireinit.bits[i + lhs_c.offset];
if (initbit != State::Sx && initbit != value[i])
log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
initbit = value[i];
}
log(" Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
}
offset += lhs_c.width;
}
@ -100,7 +115,7 @@ struct ProcInitPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing PROC_INIT pass (extract init attributes).\n");
log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
extra_args(args, 1, design);

2
passes/proc/proc_mux.cc
View File

@ -391,7 +391,7 @@ struct ProcMuxPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
extra_args(args, 1, design);

2
passes/proc/proc_rmdead.cc
View File

@ -76,7 +76,7 @@ struct ProcRmdeadPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
extra_args(args, 1, design);

2
passes/sat/eval.cc
View File

@ -389,7 +389,7 @@ struct EvalPass : public Pass {
std::vector<std::string> shows, tables;
bool set_undef = false;
log_header("Executing EVAL pass (evaluate the circuit given an input).\n");
log_header(design, "Executing EVAL pass (evaluate the circuit given an input).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/sat/expose.cc
View File

@ -262,7 +262,7 @@ struct ExposePass : public Pass {
bool flag_evert_dff = false;
std::string sep = ".";
log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n");
log_header(design, "Executing EXPOSE pass (exposing internal signals as outputs).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
passes/sat/freduce.cc
View File

@ -798,7 +798,7 @@ struct FreducePass : public Pass {
inv_mode = false;
dump_prefix = std::string();
log_header("Executing FREDUCE pass (perform functional reduction).\n");
log_header(design, "Executing FREDUCE pass (perform functional reduction).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

4
passes/sat/miter.cc
View File

@ -32,7 +32,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
bool flag_make_assert = false;
bool flag_flatten = false;
log_header("Executing MITER pass (creating miter circuit).\n");
log_header(design, "Executing MITER pass (creating miter circuit).\n");
size_t argidx;
for (argidx = 2; argidx < args.size(); argidx++)
@ -264,7 +264,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
bool flag_make_outputs = false;
bool flag_flatten = false;
log_header("Executing MITER pass (creating miter circuit).\n");
log_header(design, "Executing MITER pass (creating miter circuit).\n");
size_t argidx;
for (argidx = 2; argidx < args.size(); argidx++)

2
passes/sat/sat.cc
View File

@ -1073,7 +1073,7 @@ struct SatPass : public Pass {
int tempinduct_skip = 0, stepsize = 1;
std::string vcd_file_name, json_file_name, cnf_file_name;
log_header("Executing SAT pass (solving SAT problems in the circuit).\n");
log_header(design, "Executing SAT pass (solving SAT problems in the circuit).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

10
passes/techmap/abc.cc
View File

@ -616,7 +616,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (!cleanup)
tempdir_name[0] = tempdir_name[4] = '_';
tempdir_name = make_temp_dir(tempdir_name);
log_header("Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str());
@ -834,7 +834,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (count_output > 0)
{
log_header("Executing ABC.\n");
log_header(design, "Executing ABC.\n");
buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
f = fopen(buffer.c_str(), "wt");
@ -904,7 +904,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
ifs.close();
log_header("Re-integrating ABC results.\n");
log_header(design, "Re-integrating ABC results.\n");
RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `netlist'.\n");
@ -1299,7 +1299,7 @@ struct AbcPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing ABC pass (technology mapping using ABC).\n");
log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
log_push();
#ifdef ABCEXTERNAL
@ -1599,7 +1599,7 @@ struct AbcPass : public Pass {
assigned_cells_reverse[cell] = key;
}
log_header("Summary of detected clock domains:\n");
log_header(design, "Summary of detected clock domains:\n");
for (auto &it : assigned_cells)
log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),

2
passes/techmap/aigmap.cc
View File

@ -41,7 +41,7 @@ struct AigmapPass : public Pass {
{
bool nand_mode = false;
log_header("Executing AIGMAP pass (map logic to AIG).\n");
log_header(design, "Executing AIGMAP pass (map logic to AIG).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
passes/techmap/alumacc.cc
View File

@ -544,7 +544,7 @@ struct AlumaccPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing ALUMACC pass (create $alu and $macc cells).\n");
log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

2
passes/techmap/dff2dffe.cc
View File

@ -285,7 +285,7 @@ struct Dff2dffePass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
bool unmap_mode = false;
dict<IdString, IdString> direct_dict;

2
passes/techmap/dffinit.cc
View File

@ -41,7 +41,7 @@ struct DffinitPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing DFFINIT pass (set INIT param on FF cells).\n");
log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
dict<IdString, dict<IdString, IdString>> ff_types;

2
passes/techmap/dfflibmap.cc
View File

@ -547,7 +547,7 @@ struct DfflibmapPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
std::string liberty_file;
bool prepare_mode = false;

2
passes/techmap/dffsr2dff.cc
View File

@ -188,7 +188,7 @@ struct Dffsr2dffPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n");
log_header(design, "Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

10
passes/techmap/extract.cc
View File

@ -442,7 +442,7 @@ struct ExtractPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing EXTRACT pass (map subcircuits to cells).\n");
log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n");
log_push();
SubCircuitSolver solver;
@ -627,7 +627,7 @@ struct ExtractPass : public Pass {
std::map<std::string, RTLIL::Module*> needle_map, haystack_map;
std::vector<RTLIL::Module*> needle_list;
log_header("Creating graphs for SubCircuit library.\n");
log_header(design, "Creating graphs for SubCircuit library.\n");
if (!mine_mode)
for (auto &mod_it : map->modules_) {
@ -654,7 +654,7 @@ struct ExtractPass : public Pass {
if (!mine_mode)
{
std::vector<SubCircuit::Solver::Result> results;
log_header("Running solver from SubCircuit library.\n");
log_header(design, "Running solver from SubCircuit library.\n");
std::sort(needle_list.begin(), needle_list.end(), compareSortNeedleList);
@ -667,7 +667,7 @@ struct ExtractPass : public Pass {
if (results.size() > 0)
{
log_header("Substitute SubCircuits with cells.\n");
log_header(design, "Substitute SubCircuits with cells.\n");
for (int i = 0; i < int(results.size()); i++) {
auto &result = results[i];
@ -688,7 +688,7 @@ struct ExtractPass : public Pass {
{
std::vector<SubCircuit::Solver::MineResult> results;
log_header("Running miner from SubCircuit library.\n");
log_header(design, "Running miner from SubCircuit library.\n");
solver.mine(results, mine_cells_min, mine_cells_max, mine_min_freq, mine_limit_mod);
map = new RTLIL::Design;

2
passes/techmap/hilomap.cc
View File

@ -76,7 +76,7 @@ struct HilomapPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing HILOMAP pass (mapping to constant drivers).\n");
log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n");
hicell_celltype = std::string();
hicell_portname = std::string();

2
passes/techmap/iopadmap.cc
View File

@ -68,7 +68,7 @@ struct IopadmapPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
std::string inpad_celltype, inpad_portname, inpad_portname2;
std::string outpad_celltype, outpad_portname, outpad_portname2;

2
passes/techmap/lut2mux.cc
View File

@ -67,7 +67,7 @@ struct Lut2muxPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

2
passes/techmap/maccmap.cc
View File

@ -379,7 +379,7 @@ struct MaccmapPass : public Pass {
{
bool unmap_mode = false;
log_header("Executing MACCMAP pass (map $macc cells).\n");
log_header(design, "Executing MACCMAP pass (map $macc cells).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {

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